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<title>CPUID—CPU Identification </title></head>
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<h1>CPUID—CPU Identification</h1>
<table>
<tr>
<th>Opcode</th>
<th>Instruction</th>
<th>Op/En</th>
<th>64-Bit Mode</th>
<th>Compat/Leg Mode</th>
<th>Description</th></tr>
<tr>
<td>0F A2</td>
<td>CPUID</td>
<td>NP</td>
<td>Valid</td>
<td>Valid</td>
<td>Returns processor identification and feature information to the EAX, EBX, ECX, and EDX registers, as determined by input entered in EAX (in some cases, ECX as well).</td></tr></table>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td>
<td>Operand 4</td></tr>
<tr>
<td>NP</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td></tr></table>
<h2>Description</h2>
<p>The ID flag (bit 21) in the EFLAGS register indicates support for the CPUID instruction. If a software procedure can set and clear this flag, the processor executing the procedure supports the CPUID instruction. This instruction operates the same in non-64-bit modes and 64-bit mode.</p>
<p>CPUID returns processor identification and feature information in the EAX, EBX, ECX, and EDX registers.<sup>1</sup> The instruction’s output is dependent on the contents of the EAX register upon execution (in some cases, ECX as well). For example, the following pseudocode loads EAX with 00H and causes CPUID to return a Maximum Return Value and the Vendor Identification String in the appropriate registers:</p>
<p>MOV EAX, 00H</p>
<p>CPUID</p>
<p>Table 3-8 shows information returned, depending on the initial value loaded into the EAX register.</p>
<p>Two types of information are returned: basic and extended function information. If a value entered for CPUID.EAX is higher than the maximum input value for basic or extended function for that processor then the data for the highest basic information leaf is returned. For example, using the Intel Core i7 processor, the following is true:</p>
<p>CPUID.EAX = 05H (* Returns MONITOR/MWAIT leaf. *)</p>
<p>CPUID.EAX = 0AH (* Returns Architectural Performance Monitoring leaf. *)</p>
<p>CPUID.EAX = 0BH (* Returns Extended Topology Enumeration leaf. *)</p>
<p>CPUID.EAX = 0CH (* INVALID: Returns the same information as CPUID.EAX = 0BH. *)</p>
<p>CPUID.EAX = 80000008H (* Returns linear/physical address size data. *)</p>
<p>CPUID.EAX = 8000000AH (* INVALID: Returns same information as CPUID.EAX = 0BH. *)</p>
<p>If a value entered for CPUID.EAX is less than or equal to the maximum input value and the leaf is not supported on that processor then 0 is returned in all the registers.</p>
<p>When CPUID returns the highest basic leaf information as a result of an invalid input EAX value, any dependence on input ECX value in the basic leaf is honored.</p>
<p>CPUID can be executed at any privilege level to serialize instruction execution. Serializing instruction execution guarantees that any modifications to flags, registers, and memory for previous instructions are completed before the next instruction is fetched and executed.</p>
<p><strong>See also:</strong></p>
<p>“Serializing Instructions” in Chapter 8, “Multiple-Processor Management,” in the <em>Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A</em>.</p>
<p>“Caching Translation Information” in Chapter 4, “Paging,” in the <em>Intel® 64 and IA-32 Architectures Software Devel-oper’s Manual, Volume 3A</em>.</p>
<p>1.</p>
<p>On Intel 64 processors, CPUID clears the high 32 bits of the RAX/RBX/RCX/RDX registers in all modes.</p>
<h3>Table 3-8.  Information Returned by CPUID Instruction</h3>
<p><strong>Initial EAX</strong></p>
<p><strong>Value</strong></p>
<p><strong>Information Provided about the Processor</strong></p>
<p><em>Basic CPUID Information</em></p>
<p>0H</p>
<p>EAX</p>
<p>Maximum Input Value for Basic CPUID Information.</p>
<p>EBX</p>
<p>“Genu”</p>
<p>ECX</p>
<p>“ntel”</p>
<p>EDX</p>
<p>“ineI”</p>
<p>01H</p>
<p>EAX</p>
<p>Version Information: Type, Family, Model, and Stepping ID (see Figure 3-6).</p>
<p>EBX</p>
<p>Bits 07 - 00: Brand Index. Bits 15 - 08: CLFLUSH line size (Value ∗ 8 = cache line size in bytes; used also by CLFLUSHOPT). Bits 23 - 16: Maximum number of addressable IDs for logical processors in this physical package*. Bits 31 - 24: Initial APIC ID.</p>
<p>ECX</p>
<p>Feature Information (see Figure 3-7 and Table 3-10).</p>
<p>EDX</p>
<p>Feature Information (see Figure 3-8 and Table 3-11).</p>
<p><strong>NOTES:</strong></p>
<p>*</p>
<p>The nearest power-of-2 integer that is not smaller than EBX[23:16] is the number of unique initial APIC IDs reserved for addressing different logical processors in a physical package. This field is only valid if CPUID.1.EDX.HTT[bit 28]= 1.</p>
<p>02H</p>
<p>EAX</p>
<p>Cache and TLB Information (see Table 3-12).</p>
<p>EBX</p>
<p>Cache and TLB Information.</p>
<p>ECX</p>
<p>Cache and TLB Information.</p>
<p>EDX</p>
<p>Cache and TLB Information.</p>
<p>03H</p>
<p>EAX</p>
<p>Reserved.</p>
<p>EBX</p>
<p>Reserved.</p>
<p>ECX</p>
<p>Bits 00 - 31 of 96 bit processor serial number. (Available in Pentium III processor only; otherwise, the value in this register is reserved.)</p>
<p>EDX</p>
<p>Bits 32 - 63 of 96 bit processor serial number. (Available in Pentium III processor only; otherwise, the value in this register is reserved.)</p>
<p><strong>NOTES:</strong></p>
<p>Processor serial number (PSN) is not supported in the Pentium 4 processor or later. On all models, use the PSN flag (returned using CPUID) to check for PSN support before accessing the feature.</p>
<p>CPUID leaves above 2 and below 80000000H are visible only when IA32_MISC_ENABLE[bit 22] has its default value of 0.</p>
<p><em>Deterministic Cache Parameters Leaf</em></p>
<p><strong>NOTES:</strong></p>
<p>04H</p>
<p>Leaf 04H output depends on the initial value in ECX.*</p>
<p>See also: “INPUT EAX = 04H: Returns Deterministic Cache Parameters for Each Level” on page 213.</p>
<p>EAX</p>
<p>Bits 04 - 00: Cache Type Field.</p>
<p>0 = Null - No more caches. 1 = Data Cache. 2 = Instruction Cache. 3 = Unified Cache. 4-31 = Reserved.</p>
<h3>Table 3-8.  Information Returned by CPUID Instruction (Contd.)</h3>
<table>
<tr>
<td>
<p><strong>Initial EAX</strong></p>
<p><strong>Value</strong></p></td>
<th>Information Provided about the Processor</th></tr>
<tr>
<td></td>
<td>
<p>Bits 07 - 05: Cache Level (starts at 1). Bit 08: Self Initializing cache level (does not need SW initialization). Bit 09: Fully Associative cache.</p>
<p>Bits 13 - 10: Reserved. Bits 25 - 14: Maximum number of addressable IDs for logical processors sharing this cache**,</p>
<p>***.</p>
<p>Bits 31 - 26: Maximum number of addressable IDs for processor cores in the physical package**,</p>
<p>****,</p>
<p>*****.</p>
<p>EBX</p>
<p>Bits 11 - 00: L = System Coherency Line Size**. Bits 21 - 12: P = Physical Line partitions**. Bits 31 - 22: W = Ways of associativity**.</p>
<p>ECX</p>
<p>Bits 31-00: S = Number of Sets**.</p>
<p>EDX</p>
<p>Bit 00: Write-Back Invalidate/Invalidate.</p>
<p>0 = WBINVD/INVD from threads sharing this cache acts upon lower level caches for threads sharing this cache. 1 = WBINVD/INVD is not guaranteed to act upon lower level caches of non-originating threads sharing this cache.</p>
<p>Bit 01: Cache Inclusiveness.</p>
<p>0 = Cache is not inclusive of lower cache levels. 1 = Cache is inclusive of lower cache levels.</p>
<p>Bit 02: Complex Cache Indexing.</p>
<p>0 = Direct mapped cache. 1 = A complex function is used to index the cache, potentially using all address bits.</p>
<p>Bits 31 - 03: Reserved = 0.</p></td></tr>
<tr>
<td></td>
<td></td></tr>
<tr>
<td></td>
<td></td></tr></table>
<p><strong>NOTES:</strong></p>
<p>* If ECX contains an invalid sub leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf index n+1 is invalid if sub-</p>
<p>leaf n returns EAX[4:0] as 0.</p>
<p>** Add one to the return value to get the result.</p>
<p>***The nearest power-of-2 integer that is not smaller than (1 + EAX[25:14]) is the number of unique ini-</p>
<p>tial APIC IDs reserved for addressing different logical processors sharing this cache.</p>
<p>**** The nearest power-of-2 integer that is not smaller than (1 + EAX[31:26]) is the number of unique</p>
<p>Core_IDs reserved for addressing different processor cores in a physical package. Core ID is a subset of bits of the initial APIC ID.</p>
<p>***** The returned value is constant for valid initial values in ECX. Valid ECX values start from 0.</p>
<p><em>MONITOR/MWAIT Leaf</em></p>
<p>05H</p>
<p>EAX</p>
<p>Bits 15 - 00: Smallest monitor-line size in bytes (default is processor's monitor granularity). Bits 31 - 16: Reserved = 0.</p>
<p>EBX</p>
<p>Bits 15 - 00: Largest monitor-line size in bytes (default is processor's monitor granularity). Bits 31 - 16: Reserved = 0.</p>
<p>ECX</p>
<p>Bit 00: Enumeration of Monitor-Mwait extensions (beyond EAX and EBX registers) supported.</p>
<p>Bit 01: Supports treating interrupts as break-event for MWAIT, even when interrupts disabled.</p>
<p>Bits 31 - 02: Reserved.</p>
<h3>Table 3-8.  Information Returned by CPUID Instruction (Contd.)</h3>
<table>
<tr>
<td>
<p><strong>Initial EAX</strong></p>
<p><strong>Value</strong></p></td>
<th>Information Provided about the Processor</th></tr>
<tr>
<td></td>
<td>
<p>EDX</p>
<p>Bits 03 - 00: Number of C0* sub C-states supported using MWAIT. Bits 07 - 04: Number of C1* sub C-states supported using MWAIT. Bits 11 - 08: Number of C2* sub C-states supported using MWAIT. Bits 15 - 12: Number of C3* sub C-states supported using MWAIT. Bits 19 - 16: Number of C4* sub C-states supported using MWAIT. Bits 23 - 20: Number of C5* sub C-states supported using MWAIT. Bits 27 - 24: Number of C6* sub C-states supported using MWAIT. Bits 31 - 28: Number of C7* sub C-states supported using MWAIT.</p>
<p><strong>NOTE:</strong></p>
<p>*  The definition of C0 through C7 states for MWAIT extension are processor-specific C-states, not ACPI C-</p>
<p>states.</p></td></tr>
<tr>
<td></td>
<td><em>Thermal and Power Management Leaf</em></td></tr>
<tr>
<td>06H</td>
<td>
<p>EAX</p>
<p>Bit 00: Digital temperature sensor is supported if set. Bit 01: Intel Turbo Boost Technology Available (see description of IA32_MISC_ENABLE[38]). Bit 02: ARAT. APIC-Timer-always-running feature is supported if set. Bit 03: Reserved. Bit 04: PLN. Power limit notification controls are supported if set. Bit 05: ECMD. Clock modulation duty cycle extension is supported if set. Bit 06: PTM. Package thermal management is supported if set. Bit 07: HWP. HWP base registers (IA32_PM_ENABLE[bit 0], IA32_HWP_CAPABILITIES, IA32_HWP_REQUEST, IA32_HWP_STATUS) are supported if set. Bit 08: HWP_Notification. IA32_HWP_INTERRUPT MSR is supported if set. Bit 09: HWP_Activity_Window. IA32_HWP_REQUEST[bits 41:32] is supported if set. Bit 10: HWP_Energy_Performance_Preference. IA32_HWP_REQUEST[bits 31:24] is supported if set. Bit 11: HWP_Package_Level_Request. IA32_HWP_REQUEST_PKG MSR is supported if set. Bit 12: Reserved. Bit 13: HDC. HDC base registers IA32_PKG_HDC_CTL, IA32_PM_CTL1, IA32_THREAD_STALL MSRs are supported if set. Bits 31 - 15: Reserved.</p>
<p>EBX</p>
<p>Bits 03 - 00: Number of Interrupt Thresholds in Digital Thermal Sensor. Bits 31 - 04: Reserved.</p>
<p>ECX</p>
<p>Bit 00: Hardware Coordination Feedback Capability (Presence of IA32_MPERF and IA32_APERF). The capability to provide a measure of delivered processor performance (since last reset of the counters), as a percentage of the expected processor performance when running at the TSC frequency. Bits 02 - 01: Reserved = 0. Bit 03: The processor supports performance-energy bias preference if CPUID.06H:ECX.SETBH[bit 3] is set and it also implies the presence of a new architectural MSR called IA32_ENERGY_PERF_BIAS (1B0H). Bits 31 - 04: Reserved = 0.</p>
<p>EDX</p>
<p>Reserved = 0.</p></td></tr></table>
<h3>Table 3-8.  Information Returned by CPUID Instruction (Contd.)</h3>
<table>
<tr>
<td>
<p><strong>Initial EAX</strong></p>
<p><strong>Value</strong></p></td>
<th>Information Provided about the Processor</th></tr>
<tr>
<td></td>
<td><em>Structured Extended Feature Flags Enumeration Leaf (Output depends on ECX input value)</em></td></tr>
<tr>
<td>07H</td>
<td>
<p>Sub-leaf 0 (Input ECX = 0). *</p>
<p>EAX</p>
<p>Bits 31 - 00: Reports the maximum input value for supported leaf 7 sub-leaves.</p>
<p>EBX</p>
<p>Bit 00: FSGSBASE. Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE if 1. Bit 01: IA32_TSC_ADJUST MSR is supported if 1. Bit 02: SGX. Supports Intel® Software Guard Extensions (Intel® SGX Extensions) if 1. Bit 03: BMI1. Bit 04: HLE. Bit 05: AVX2. Bit 06: FDP_EXCPTN_ONLY. x87 FPU Data Pointer updated only on x87 exceptions if 1. Bit 07: SMEP. Supports Supervisor-Mode Execution Prevention if 1. Bit 08: BMI2. Bit 09: Supports Enhanced REP MOVSB/STOSB if 1. Bit 10: INVPCID. If 1, supports INVPCID instruction for system software that manages process-context identifiers. Bit 11: RTM. Bit 12: RDT-M. Supports Intel® Resource Director Technology (Intel® RDT) Monitoring capability if 1. Bit 13: Deprecates FPU CS and FPU DS values if 1. Bit 14: MPX. Supports Intel® Memory Protection Extensions if 1. Bit 15: RDT-A. Supports Intel® Resource Director Technology (Intel® RDT) Allocation capability if 1. Bits 17:16: Reserved. Bit 18: RDSEED. Bit 19: ADX. Bit 20: SMAP. Supports Supervisor-Mode Access Prevention (and the CLAC/STAC instructions) if 1. Bits 22 - 21: Reserved. Bit 23: CLFLUSHOPT. Bit 24: Reserved. Bit 25: Intel Processor Trace. Bits 28 - 26: Reserved. Bit 29: SHA. supports Intel® Secure Hash Algorithm Extensions (Intel® SHA Extensions) if 1. Bits 31 - 30: Reserved.</p>
<p>ECX</p>
<p>Bit 00: PREFETCHWT1. Bit 01: Reserved. Bit 02: UMIP. Supports user-mode instruction prevention if 1. Bit 03: PKU. Supports protection keys for user-mode pages if 1. Bit 04: OSPKE. If 1, OS has set CR4.PKE to enable protection keys (and the RDPKRU/WRPKRU instruc-tions). Bits 16 - 5: Reserved. Bits 21 - 17: The value of MAWAU used by the BNDLDX and BNDSTX instructions in 64-bit mode. Bit 22: RDPID. Supports Read Processor ID if 1. Bits 29 - 23: Reserved. Bit 30: SGX_LC. Supports SGX Launch Configuration if 1. Bit 31: Reserved.</p>
<p>EDX</p>
<p>Reserved.</p>
<p><strong>NOTE:</strong></p>
<p>* If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf index n is invalid if n</p>
<p>exceeds the value that sub-leaf 0 returns in EAX.</p></td></tr></table>
<h3>Table 3-8.  Information Returned by CPUID Instruction (Contd.)</h3>
<table>
<tr>
<td>
<p><strong>Initial EAX</strong></p>
<p><strong>Value</strong></p></td>
<th>Information Provided about the Processor</th></tr>
<tr>
<td></td>
<td><em>Direct Cache Access Information Leaf</em></td></tr>
<tr>
<td>09H</td>
<td>
<p>EAX</p>
<p>Value of bits [31:0] of IA32_PLATFORM_DCA_CAP MSR (address 1F8H).</p>
<p>EBX</p>
<p>Reserved.</p>
<p>ECX</p>
<p>Reserved.</p>
<p>EDX</p>
<p>Reserved.</p></td></tr>
<tr>
<td></td>
<td><em>Architectural Performance Monitoring Leaf</em></td></tr>
<tr>
<td>0AH</td>
<td>
<p>EAX</p>
<p>Bits 07 - 00: Version ID of architectural performance monitoring. Bits 15 - 08: Number of general-purpose performance monitoring counter per logical processor. Bits 23 - 16: Bit width of general-purpose, performance monitoring counter. Bits 31 - 24: Length of EBX bit vector to enumerate architectural performance monitoring events.</p>
<p>EBX</p>
<p>Bit 00: Core cycle event not available if 1. Bit 01: Instruction retired event not available if 1. Bit 02: Reference cycles event not available if 1. Bit 03: Last-level cache reference event not available if 1. Bit 04: Last-level cache misses event not available if 1. Bit 05: Branch instruction retired event not available if 1. Bit 06: Branch mispredict retired event not available if 1. Bits 31 - 07: Reserved = 0.</p>
<p>ECX</p>
<p>Reserved = 0.</p>
<p>EDX</p>
<p>Bits 04 - 00: Number of fixed-function performance counters (if Version ID &gt; 1). Bits 12 - 05: Bit width of fixed-function performance counters (if Version ID &gt; 1). Reserved = 0.</p></td></tr>
<tr>
<td></td>
<td><em>Extended Topology Enumeration Leaf</em></td></tr>
<tr>
<td></td>
<td></td></tr></table>
<p><strong>NOTES:</strong></p>
<p>0BH</p>
<p>Most of Leaf 0BH output depends on the initial value in ECX.</p>
<p>The EDX output of leaf 0BH is always valid and does not vary with input value in ECX.</p>
<p>Output value in ECX[7:0] always equals input value in ECX[7:0].</p>
<p>For sub-leaves that return an invalid level-type of 0 in ECX[15:8]; EAX and EBX will return 0.</p>
<p>  If an input value n in ECX returns the invalid level-type of 0 in ECX[15:8], other input values with ECX &gt;</p>
<p>n also return 0 in ECX[15:8].</p>
<p>EAX</p>
<p>Bits 04 - 00: Number of bits to shift right on x2APIC ID to get a unique topology ID of the next level type*. All logical processors with the same next level ID share current level. Bits 31 - 05: Reserved.</p>
<p>EBX</p>
<p>Bits 15 - 00: Number of logical processors at this level type. The number reflects configuration as shipped by Intel**. Bits 31- 16: Reserved.</p>
<p>ECX</p>
<p>Bits 07 - 00: Level number. Same value in ECX input. Bits 15 - 08: Level type***. Bits 31 - 16: Reserved.</p>
<p>EDX</p>
<p>Bits 31- 00: x2APIC ID the current logical processor.</p>
<p><strong>NOTES: * Software should use this field (EAX[4:0]) to enumerate processor topology of the system.</strong></p>
<h3>Table 3-8.  Information Returned by CPUID Instruction (Contd.)</h3>
<table>
<tr>
<td>
<p><strong>Initial EAX</strong></p>
<p><strong>Value</strong></p></td>
<th>Information Provided about the Processor</th></tr>
<tr>
<td></td>
<td>
<p>** Software must not use EBX[15:0] to enumerate processor topology of the system. This value in this field (EBX[15:0]) is only intended for display/diagnostic purposes. The actual number of logical processors available to BIOS/OS/Applications may be different from the value of EBX[15:0], depending on software and platform hardware configurations.</p>
<p>*** The value of the “level type” field is not related to level numbers in any way, higher “level type” val-ues do not mean higher levels. Level type field has the following encoding: 0: Invalid. 1: SMT. 2: Core. 3-255: Reserved.</p></td></tr>
<tr>
<td></td>
<td><em>Processor Extended State Enumeration Main Leaf (EAX = 0DH, ECX = 0)</em></td></tr>
<tr>
<td></td>
<td></td></tr>
<tr>
<td></td>
<td></td></tr>
<tr>
<td></td>
<td></td></tr></table>
<p><strong>NOTES:</strong></p>
<p>0DH</p>
<p>Leaf 0DH main leaf (ECX = 0).</p>
<p>EAX</p>
<p>Bits 31 - 00: Reports the supported bits of the lower 32 bits of XCR0. XCR0[n] can be set to 1 only if EAX[n] is 1. Bit 00: x87 state. Bit 01: SSE state. Bit 02: AVX state. Bits 04 - 03: MPX state. Bits 07 - 05: AVX-512 state. Bit 08: Used for IA32_XSS. Bit 09: PKRU state. Bits 31 - 10: Reserved.</p>
<p>EBX</p>
<p>Bits 31 - 00: Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save area) required by enabled features in XCR0. May be different than ECX if some features at the end of the XSAVE save area are not enabled.</p>
<p>ECX</p>
<p>Bit 31 - 00: Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save area) of the XSAVE/XRSTOR save area required by all supported features in the processor, i.e., all the valid bit fields in XCR0.</p>
<p>EDX</p>
<p>Bit 31 - 00: Reports the supported bits of the upper 32 bits of XCR0. XCR0[n+32] can be set to 1 only if EDX[n] is 1. Bits 31 - 00: Reserved.</p>
<p><em>Processor Extended State Enumeration Sub-leaf (EAX = 0DH, ECX = 1)</em></p>
<p>0DH</p>
<p>EAX</p>
<p>Bit 00: XSAVEOPT is available. Bit 01: Supports XSAVEC and the compacted form of XRSTOR if set. Bit 02: Supports XGETBV with ECX = 1 if set. Bit 03: Supports XSAVES/XRSTORS and IA32_XSS if set. Bits 31 - 04: Reserved.</p>
<p>EBX</p>
<p>Bits 31 - 00: The size in bytes of the XSAVE area containing all states enabled by XCRO | IA32_XSS.</p>
<p>ECX</p>
<p>Bits 31 - 00: Reports the supported bits of the lower 32 bits of the IA32_XSS MSR. IA32_XSS[n] can be set to 1 only if ECX[n] is 1. Bits 07 - 00: Used for XCR0. Bit 08: PT state. Bit 09: Used for XCR0. Bits 31 - 10: Reserved.</p>
<p>EDX</p>
<p>Bits 31 - 00: Reports the supported bits of the upper 32 bits of the IA32_XSS MSR. IA32_XSS[n+32] can be set to 1 only if EDX[n] is 1. Bits 31 - 00: Reserved.</p>
<h3>Table 3-8.  Information Returned by CPUID Instruction (Contd.)</h3>
<table>
<tr>
<td>
<p><strong>Initial EAX</strong></p>
<p><strong>Value</strong></p></td>
<th>Information Provided about the Processor</th></tr>
<tr>
<td></td>
<td><em>Processor Extended State Enumeration Sub-leaves (EAX = 0DH, ECX = n, n &gt; 1)</em></td></tr>
<tr>
<td></td>
<td></td></tr>
<tr>
<td></td>
<td></td></tr>
<tr>
<td></td>
<td></td></tr>
<tr>
<td></td>
<td></td></tr>
<tr>
<td></td>
<td></td></tr></table>
<p><strong>NOTES:</strong></p>
<p>0DH</p>
<p>Leaf 0DH output depends on the initial value in ECX.</p>
<p>Each sub-leaf index (starting at position 2) is supported if it corresponds to a supported bit in either the XCR0 register or the IA32_XSS MSR.</p>
<p>* If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf n (0 ≤ n ≤ 31) is invalid</p>
<p>if sub-leaf 0 returns 0 in EAX[n] and sub-leaf 1 returns 0 in ECX[n]. Sub-leaf n (32 ≤ n ≤ 63) is invalid if sub-leaf 0 returns 0 in EDX[n-32] and sub-leaf 1 returns 0 in EDX[n-32].</p>
<p>EAX</p>
<p>Bits 31 - 0: The size in bytes (from the offset specified in EBX) of the save area for an extended state feature associated with a valid sub-leaf index, <em>n</em>.</p>
<p>EBX</p>
<p>Bits 31 - 0: The offset in bytes of this extended state component’s save area from the beginning of the XSAVE/XRSTOR area. This field reports 0 if the sub-leaf index, n, does not map to a valid bit in the XCR0 register*.</p>
<p>ECX</p>
<p>Bit 00 is set if the bit n (corresponding to the sub-leaf index) is supported in the IA32_XSS MSR; it is clear if bit n is instead supported in XCR0. Bit 01 is set if, when the compacted format of an XSAVE area is used, this extended state component located on the next 64-byte boundary following the preceding state component (otherwise, it is located immediately following the preceding state component). Bits 31 - 02 are reserved. This field reports 0 if the sub-leaf index, n, is invalid*.</p>
<p>EDX</p>
<p>This field reports 0 if the sub-leaf index, <em>n</em>, is invalid*; otherwise it is reserved.</p>
<p><em>Intel Resource Director Technology (Intel RDT) Monitoring Enumeration Sub-leaf (EAX = 0FH, ECX = 0)</em></p>
<p><strong>NOTES:</strong></p>
<p>0FH</p>
<p>Leaf 0FH output depends on the initial value in ECX.</p>
<p>Sub-leaf index 0 reports valid resource type starting at bit position 1 of EDX.</p>
<p>EAX</p>
<p>Reserved.</p>
<p>EBX</p>
<p>Bits 31 - 00: Maximum range (zero-based) of RMID within this physical processor of all types.</p>
<p>ECX</p>
<p>Reserved.</p>
<p>EDX</p>
<p>Bit 00: Reserved. Bit 01: Supports L3 Cache Intel RDT Monitoring if 1. Bits 31 - 02: Reserved.</p>
<p><em>L3 Cache Intel RDT Monitoring Capability Enumeration Sub-leaf (EAX = 0FH, ECX = 1)</em></p>
<p><strong>NOTES:</strong></p>
<p>0FH</p>
<p>Leaf 0FH output depends on the initial value in ECX.</p>
<p>EAX</p>
<p>Reserved.</p>
<p>EBX</p>
<p>Bits 31 - 00: Conversion factor from reported IA32_QM_CTR value to occupancy metric (bytes).</p>
<p>ECX</p>
<p>Maximum range (zero-based) of RMID of this resource type.</p>
<p>EDX</p>
<p>Bit 00: Supports L3 occupancy monitoring if 1. Bit 01: Supports L3 Total Bandwidth monitoring if 1. Bit 02: Supports L3 Local Bandwidth monitoring if 1. Bits 31 - 03: Reserved.</p>
<h3>Table 3-8.  Information Returned by CPUID Instruction (Contd.)</h3>
<table>
<tr>
<td>
<p><strong>Initial EAX</strong></p>
<p><strong>Value</strong></p></td>
<th>Information Provided about the Processor</th></tr>
<tr>
<td></td>
<td><em>Intel Resource Director Technology (Intel RDT) Allocation Enumeration Sub-leaf (EAX = 10H, ECX = 0)</em></td></tr>
<tr>
<td></td>
<td></td></tr>
<tr>
<td></td>
<td></td></tr>
<tr>
<td></td>
<td></td></tr>
<tr>
<td></td>
<td></td></tr>
<tr>
<td></td>
<td></td></tr>
<tr>
<td></td>
<td></td></tr>
<tr>
<td></td>
<td></td></tr></table>
<p><strong>NOTES:</strong></p>
<p>10H</p>
<p>Leaf 10H output depends on the initial value in ECX.</p>
<p>Sub-leaf index 0 reports valid resource identification (ResID) starting at bit position 1 of EBX.</p>
<p>EAX</p>
<p>Reserved.</p>
<p>EBX</p>
<p>Bit 00: Reserved. Bit 01: Supports L3 Cache Allocation Technology if 1. Bit 02: Supports L2 Cache Allocation Technology if 1. Bits 31 - 03: Reserved.</p>
<p>ECX</p>
<p>Reserved.</p>
<p>EDX</p>
<p>Reserved.</p>
<p><em>L3 Cache Allocation Technology Enumeration Sub-leaf (EAX = 10H, ECX = ResID =1)</em></p>
<p><strong>NOTES:</strong></p>
<p>10H</p>
<p>Leaf 10H output depends on the initial value in ECX.</p>
<p>EAX</p>
<p>Bits 4 - 00: Length of the capacity bit mask for the corresponding ResID using minus-one notation. Bits 31 - 05: Reserved.</p>
<p>EBX</p>
<p>Bits 31 - 00: Bit-granular map of isolation/contention of allocation units.</p>
<p>ECX</p>
<p>Bit 00: Reserved. Bit 01: Updates of COS should be infrequent if 1. Bit 02: Code and Data Prioritization Technology supported if 1. Bits 31 - 03: Reserved.</p>
<p>EDX</p>
<p>Bits 15 - 00: Highest COS number supported for this ResID. Bits 31 - 16: Reserved.</p>
<p><em>L2 Cache Allocation Technology Enumeration Sub-leaf (EAX = 10H, ECX = ResID =2)</em></p>
<p><strong>NOTES:</strong></p>
<p>10H</p>
<p>Leaf 10H output depends on the initial value in ECX.</p>
<p>EAX</p>
<p>Bits 4 - 00: Length of the capacity bit mask for the corresponding ResID using minus-one notation. Bits 31 - 05: Reserved.</p>
<p>EBX</p>
<p>Bits 31 - 00: Bit-granular map of isolation/contention of allocation units.</p>
<p>ECX</p>
<p>Bits 31 - 00: Reserved.</p>
<p>EDX</p>
<p>Bits 15 - 00: Highest COS number supported for this ResID. Bits 31 - 16: Reserved.</p>
<p><em>Intel SGX Capability Enumeration Leaf, sub-leaf 0 (EAX = 12H, ECX = 0)</em></p>
<p>12H</p>
<p><strong>NOTES:</strong></p>
<p>Leaf 12H sub-leaf 0 (ECX = 0) is supported if CPUID.(EAX=07H, ECX=0H):EBX[SGX] = 1.</p>
<p>EAX</p>
<p>Bit 00: SGX1. If 1, Indicates Intel SGX supports the collection of SGX1 leaf functions. Bit 01: SGX2. If 1, Indicates Intel SGX supports the collection of SGX2 leaf functions. Bit 31 - 02: Reserved.</p>
<p>EBX</p>
<p>Bit 31 - 00: MISCSELECT. Bit vector of supported extended SGX features.</p>
<p>ECX</p>
<p>Bit 31 - 00: Reserved.</p>
<h3>Table 3-8.  Information Returned by CPUID Instruction (Contd.)</h3>
<table>
<tr>
<td>
<p><strong>Initial EAX</strong></p>
<p><strong>Value</strong></p></td>
<th>Information Provided about the Processor</th></tr>
<tr>
<td></td>
<td>
<p>EDX</p>
<p>Bit 07 - 00: MaxEnclaveSize_Not64. The maximum supported enclave size in non-64-bit mode is 2^(EDX[7:0]). Bit 15 - 08: MaxEnclaveSize_64. The maximum supported enclave size in 64-bit mode is 2^(EDX[15:8]). Bits 31 - 16: Reserved.</p></td></tr>
<tr>
<td></td>
<td><em>Intel SGX Attributes Enumeration Leaf, sub-leaf 1 (EAX = 12H, ECX = 1)</em></td></tr>
<tr>
<td>12H</td>
<td></td></tr>
<tr>
<td></td>
<td></td></tr>
<tr>
<td></td>
<td></td></tr></table>
<p><strong>NOTES:</strong></p>
<p>Leaf 12H sub-leaf 1 (ECX = 1) is supported if CPUID.(EAX=07H, ECX=0H):EBX[SGX] = 1.</p>
<p>EAX</p>
<p>Bit 31 - 00: Reports the valid bits of SECS.ATTRIBUTES[31:0] that software can set with ECREATE.</p>
<p>EBX</p>
<p>Bit 31 - 00: Reports the valid bits of SECS.ATTRIBUTES[63:32] that software can set with ECREATE.</p>
<p>ECX</p>
<p>Bit 31 - 00: Reports the valid bits of SECS.ATTRIBUTES[95:64] that software can set with ECREATE.</p>
<p>EDX</p>
<p>Bit 31 - 00: Reports the valid bits of SECS.ATTRIBUTES[127:96] that software can set with ECREATE.</p>
<p><em>Intel SGX EPC Enumeration Leaf, sub-leaves (EAX = 12H, ECX = 2 or higher)</em></p>
<p>12H</p>
<p><strong>NOTES:</strong></p>
<p>Leaf 12H sub-leaf 2 or higher (ECX &gt;= 2) is supported if CPUID.(EAX=07H, ECX=0H):EBX[SGX] = 1.</p>
<p>For sub-leaves (ECX = 2 or higher), definition of EDX,ECX,EBX,EAX[31:4] depends on the sub-leaf type listed below.</p>
<p>EAX</p>
<p>Bit 03 - 00: Sub-leaf Type</p>
<p>0000b: Indicates this sub-leaf is invalid. 0001b: This sub-leaf enumerates an EPC section. EBX:EAX and EDX:ECX provide information on the Enclave Page Cache (EPC) section. All other type encodings are reserved.</p>
<p>Type</p>
<p>0000b. This sub-leaf is invalid.</p>
<p>EDX:ECX:EBX:EAX return 0.</p>
<p>Type</p>
<p>0001b. This sub-leaf enumerates an EPC sections with EDX:ECX, EBX:EAX defined as follows.</p>
<p>EAX[11:04]: Reserved (enumerate 0). EAX[31:12]: Bits 31:12 of the physical address of the base of the EPC section.</p>
<p>EBX[19:00]: Bits 51:32 of the physical address of the base of the EPC section. EBX[31:20]: Reserved.</p>
<p>ECX[03:00]: EPC section property encoding defined as follows:</p>
<p>If EAX[3:0] 0000b, then all bits of the EDX:ECX pair are enumerated as 0. If EAX[3:0] 0001b, then this section has confidentiality and integrity protection. All other encodings are reserved.</p>
<p>ECX[11:04]: Reserved (enumerate 0). ECX[31:12]: Bits 31:12 of the size of the corresponding EPC section within the Processor Reserved Memory.</p>
<p>EDX[19:00]: Bits 51:32 of the size of the corresponding EPC section within the Processor Reserved Memory. EDX[31:20]: Reserved.</p>
<h3>Table 3-8.  Information Returned by CPUID Instruction (Contd.)</h3>
<table>
<tr>
<td>
<p><strong>Initial EAX</strong></p>
<p><strong>Value</strong></p></td>
<th>Information Provided about the Processor</th></tr>
<tr>
<td></td>
<td><em>Intel Processor Trace Enumeration Main Leaf (EAX = 14H, ECX = 0)</em></td></tr>
<tr>
<td>14H</td>
<td></td></tr>
<tr>
<td></td>
<td></td></tr>
<tr>
<td></td>
<td></td></tr>
<tr>
<td></td>
<td></td></tr>
<tr>
<td></td>
<td></td></tr></table>
<p><strong>NOTES:</strong></p>
<p>Leaf 14H main leaf (ECX = 0).</p>
<p>EAX</p>
<p>Bits 31 - 00: Reports the maximum sub-leaf supported in leaf 14H.</p>
<p>EBX</p>
<p>Bit 00: If 1, indicates that IA32_RTIT_CTL.CR3Filter can be set to 1, and that IA32_RTIT_CR3_MATCH MSR can be accessed. Bit 01: If 1, indicates support of Configurable PSB and Cycle-Accurate Mode. Bit 02: If 1, indicates support of IP Filtering, TraceStop filtering, and preservation of Intel PT MSRs across warm reset. Bit 03: If 1, indicates support of MTC timing packet and suppression of COFI-based packets. Bit 04: If 1, indicates support of PTWRITE. Writes can set IA32_RTIT_CTL[12] (PTWEn) and IA32_RTIT_CTL[5] (FUPonPTW), and PTWRITE can generate packets. Bit 05: If 1, indicates support of Power Event Trace. Writes can set IA32_RTIT_CTL[4] (PwrEvtEn), enabling Power Event Trace packet generation. Bit 31 - 06: Reserved.</p>
<p>ECX</p>
<p>Bit 00: If 1, Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1, hence utilizing the ToPA output scheme; IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be accessed. Bit 01: If 1, ToPA tables can hold any number of output entries, up to the maximum allowed by the Mas-kOrTableOffset field of IA32_RTIT_OUTPUT_MASK_PTRS. Bit 02: If 1, indicates support of Single-Range Output scheme. Bit 03: If 1, indicates support of output to Trace Transport subsystem. Bit 30 - 04: Reserved. Bit 31: If 1, generated packets which contain IP payloads have LIP values, which include the CS base com-ponent.</p>
<p>EDX</p>
<p>Bits 31 - 00: Reserved.</p>
<p><em>Intel Processor Trace Enumeration Sub-leaf (EAX = 14H, ECX = 1)</em></p>
<p>14H</p>
<p>EAX</p>
<p>Bits 02 - 00: Number of configurable Address Ranges for filtering. Bits 15 - 03: Reserved. Bits 31 - 16: Bitmap of supported MTC period encodings.</p>
<p>EBX</p>
<p>Bits 15 - 00: Bitmap of supported Cycle Threshold value encodings. Bit 31 - 16: Bitmap of supported Configurable PSB frequency encodings.</p>
<p>ECX</p>
<p>Bits 31 - 00: Reserved.</p>
<p>EDX</p>
<p>Bits 31 - 00: Reserved.</p>
<p><em>Time Stamp Counter/Core Crystal Clock Information-leaf</em></p>
<p><strong>NOTES:</strong></p>
<p>15H</p>
<p>If EBX[31:0] is 0, the TSC/”core crystal clock” ratio is not enumerated.</p>
<p>EBX[31:0]/EAX[31:0] indicates the ratio of the TSC frequency and the core crystal clock frequency.</p>
<p>“TSC frequency” = “core crystal clock frequency” * EBX/EAX.</p>
<p>The core crystal clock may differ from the reference clock, bus clock, or core clock frequencies.</p>
<p>EAX</p>
<p>Bits 31 - 00: An unsigned integer which is the denominator of the TSC/”core crystal clock” ratio.</p>
<p>EBX</p>
<p>Bits 31 - 00: An unsigned integer which is the numerator of the TSC/”core crystal clock” ratio.</p>
<p>ECX</p>
<p>Bits 31 - 00: Reserved = 0.</p>
<p>EDX</p>
<p>Bits 31 - 00: Reserved = 0.</p>
<h3>Table 3-8.  Information Returned by CPUID Instruction (Contd.)</h3>
<table>
<tr>
<td>
<p><strong>Initial EAX</strong></p>
<p><strong>Value</strong></p></td>
<th>Information Provided about the Processor</th></tr>
<tr>
<td></td>
<td><em>Processor Frequency Information Leaf</em></td></tr>
<tr>
<td>16H</td>
<td>
<p>EAX</p>
<p>Bits 15 - 00: Processor Base Frequency (in MHz). Bits 31 - 16: Reserved =0.</p>
<p>EBX</p>
<p>Bits 15 - 00: Maximum Frequency (in MHz). Bits 31 - 16: Reserved = 0.</p>
<p>ECX</p>
<p>Bits 15 - 00: Bus (Reference) Frequency (in MHz). Bits 31 - 16: Reserved = 0.</p>
<p>EDX</p>
<p>Reserved.</p></td></tr>
<tr>
<td></td>
<td></td></tr>
<tr>
<td></td>
<td></td></tr>
<tr>
<td></td>
<td></td></tr>
<tr>
<td></td>
<td></td></tr></table>
<p><strong>NOTES: * Data is returned from this interface in accordance with the processor's specification and does not reflect actual values. Suitable use of this data includes the display of processor information in like manner to the processor brand string and for determining the appropriate range to use when displaying processor information e.g. frequency history graphs. The returned information should not be used for any other purpose as the returned information does not accurately correlate to information / counters returned by other processor interfaces.</strong></p>
<p>While a processor may support the Processor Frequency Information leaf, fields that return a value of zero are not supported.</p>
<p><em>System-On-Chip Vendor Attribute Enumeration Main Leaf (EAX = 17H, ECX = 0)</em></p>
<p><strong>NOTES:</strong></p>
<p>17H</p>
<p>Leaf 17H main leaf (ECX = 0).</p>
<p>Leaf 17H output depends on the initial value in ECX.</p>
<p>Leaf 17H sub-leaves 1 through 3 reports SOC Vendor Brand String.</p>
<p>Leaf 17H is valid if MaxSOCID_Index &gt;= 3.</p>
<p>Leaf 17H sub-leaves 4 and above are reserved.</p>
<p>EAX</p>
<p>Bits 31 - 00: MaxSOCID_Index. Reports the maximum input value of supported sub-leaf in leaf 17H.</p>
<p>EBX</p>
<p>Bits 15 - 00: SOC Vendor ID. Bit 16: IsVendorScheme. If 1, the SOC Vendor ID field is assigned via an industry standard enumeration scheme. Otherwise, the SOC Vendor ID field is assigned by Intel. Bits 31 - 17: Reserved = 0.</p>
<p>ECX</p>
<p>Bits 31 - 00: Project ID. A unique number an SOC vendor assigns to its SOC projects.</p>
<p>EDX</p>
<p>Bits 31 - 00: Stepping ID. A unique number within an SOC project that an SOC vendor assigns.</p>
<p><em>System-On-Chip Vendor Attribute Enumeration Sub-leaf (EAX = 17H, ECX = 1..3)</em></p>
<p>17H</p>
<p>EAX</p>
<p>Bit 31 - 00: SOC Vendor Brand String. UTF-8 encoded string.</p>
<p>EBX</p>
<p>Bit 31 - 00: SOC Vendor Brand String. UTF-8 encoded string.</p>
<p>ECX</p>
<p>Bit 31 - 00: SOC Vendor Brand String. UTF-8 encoded string.</p>
<p>EDX</p>
<p>Bit 31 - 00: SOC Vendor Brand String. UTF-8 encoded string.</p>
<p><strong>NOTES:</strong></p>
<p>Leaf 17H output depends on the initial value in ECX.</p>
<p>SOC Vendor Brand String is a UTF-8 encoded string padded with trailing bytes of 00H.</p>
<p>The complete SOC Vendor Brand String is constructed by concatenating in ascending order of</p>
<p>EAX:EBX:ECX:EDX and from the sub-leaf 1 fragment towards sub-leaf 3.</p>
<h3>Table 3-8.  Information Returned by CPUID Instruction (Contd.)</h3>
<table>
<tr>
<td>
<p><strong>Initial EAX</strong></p>
<p><strong>Value</strong></p></td>
<th>Information Provided about the Processor</th></tr>
<tr>
<td></td>
<td><em>System-On-Chip Vendor Attribute Enumeration Sub-leaves (EAX = 17H, ECX &gt; MaxSOCID_Index)</em></td></tr>
<tr>
<td></td>
<td></td></tr>
<tr>
<td></td>
<td></td></tr>
<tr>
<td></td>
<td></td></tr>
<tr>
<td></td>
<td></td></tr>
<tr>
<td></td>
<td></td></tr>
<tr>
<td></td>
<td></td></tr>
<tr>
<td></td>
<td></td></tr>
<tr>
<td></td>
<td></td></tr></table>
<p><strong>NOTES:</strong></p>
<p>17H</p>
<p>Leaf 17H output depends on the initial value in ECX.</p>
<p>EAX</p>
<p>Bits 31 - 00: Reserved = 0.</p>
<p>EBX</p>
<p>Bits 31 - 00: Reserved = 0.</p>
<p>ECX</p>
<p>Bits 31 - 00: Reserved = 0.</p>
<p>EDX</p>
<p>Bits 31 - 00: Reserved = 0.</p>
<p><em>Unimplemented CPUID Leaf Functions</em></p>
<p>40000000H</p>
<p>Invalid. No existing or future CPU will return processor identification or feature information if the initial</p>
<p>-</p>
<p>EAX value is in the range 40000000H to 4FFFFFFFH.</p>
<p>4FFFFFFFH</p>
<p><em>Extended Function CPUID Information</em></p>
<p>80000000H</p>
<p>EAX</p>
<p>Maximum Input Value for Extended Function CPUID Information.</p>
<p>EBX</p>
<p>Reserved.</p>
<p>ECX</p>
<p>Reserved.</p>
<p>EDX</p>
<p>Reserved.</p>
<p>80000001H</p>
<p>EAX</p>
<p>Extended Processor Signature and Feature Bits.</p>
<p>EBX</p>
<p>Reserved.</p>
<p>ECX</p>
<p>Bit 00: LAHF/SAHF available in 64-bit mode. Bits 04 - 01: Reserved. Bit 05: LZCNT. Bits 07 - 06: Reserved. Bit 08: PREFETCHW. Bits 31 - 09: Reserved.</p>
<p>EDX</p>
<p>Bits 10 - 00: Reserved. Bit 11: SYSCALL/SYSRET available in 64-bit mode. Bits 19 - 12: Reserved = 0. Bit 20: Execute Disable Bit available. Bits 25 - 21: Reserved = 0. Bit 26: 1-GByte pages are available if 1. Bit 27: RDTSCP and IA32_TSC_AUX are available if 1. Bit 28: Reserved = 0.</p>
<p>Bit 29: Intel<em><sup>®</sup></em> 64 Architecture available if 1. Bits 31 - 30: Reserved = 0.</p>
<p>80000002H</p>
<p>EAX</p>
<p>Processor Brand String.</p>
<p>EBX</p>
<p>Processor Brand String Continued.</p>
<p>ECX</p>
<p>Processor Brand String Continued.</p>
<p>EDX</p>
<p>Processor Brand String Continued.</p>
<p>80000003H</p>
<p>EAX</p>
<p>Processor Brand String Continued.</p>
<p>EBX</p>
<p>Processor Brand String Continued.</p>
<p>ECX</p>
<p>Processor Brand String Continued.</p>
<p>EDX</p>
<p>Processor Brand String Continued.</p>
<h3>Table 3-8.  Information Returned by CPUID Instruction (Contd.)</h3>
<table>
<tr>
<td>
<p><strong>Initial EAX</strong></p>
<p><strong>Value</strong></p></td>
<th>Information Provided about the Processor</th></tr>
<tr>
<td>80000004H</td>
<td>
<p>EAX</p>
<p>Processor Brand String Continued.</p>
<p>EBX</p>
<p>Processor Brand String Continued.</p>
<p>ECX</p>
<p>Processor Brand String Continued.</p>
<p>EDX</p>
<p>Processor Brand String Continued.</p></td></tr>
<tr>
<td>80000005H</td>
<td>
<p>EAX</p>
<p>Reserved = 0.</p>
<p>EBX</p>
<p>Reserved = 0.</p>
<p>ECX</p>
<p>Reserved = 0.</p>
<p>EDX</p>
<p>Reserved = 0.</p></td></tr>
<tr>
<td>80000006H</td>
<td>
<p>EAX</p>
<p>Reserved = 0.</p>
<p>EBX</p>
<p>Reserved = 0.</p>
<p>ECX</p>
<p>Bits 07 - 00: Cache Line size in bytes. Bits 11 - 08: Reserved. Bits 15 - 12: L2 Associativity field *. Bits 31 - 16: Cache size in 1K units.</p>
<p>EDX</p>
<p>Reserved = 0.</p></td></tr>
<tr>
<td></td>
<td></td></tr>
<tr>
<td></td>
<td></td></tr></table>
<p><strong>NOTES:</strong></p>
<p>* L2 associativity field encodings:</p>
<p>00H - Disabled. 01H - Direct mapped. 02H - 2-way. 04H - 4-way. 06H - 8-way. 08H - 16-way. 0FH - Fully associative.</p>
<p>80000007H</p>
<p>EAX</p>
<p>Reserved = 0.</p>
<p>EBX</p>
<p>Reserved = 0.</p>
<p>ECX</p>
<p>Reserved = 0.</p>
<p>EDX</p>
<p>Bits 07 - 00: Reserved = 0. Bit 08: Invariant TSC available if 1. Bits 31 - 09: Reserved = 0.</p>
<p>80000008H</p>
<p>EAX</p>
<p>Linear/Physical Address size. Bits 07 - 00: #Physical Address Bits*. Bits 15 - 08: #Linear Address Bits. Bits 31 - 16: Reserved = 0.</p>
<p>EBX</p>
<p>Reserved = 0.</p>
<p>ECX</p>
<p>Reserved = 0.</p>
<p>EDX</p>
<p>Reserved = 0.</p>
<p><strong>NOTES:</strong></p>
<p>*</p>
<p>If CPUID.80000008H:EAX[7:0] is supported, the maximum physical address number supported should come from this field.</p>
<h2>INPUT EAX = 0: Returns CPUID’s Highest Value for Basic Processor Information and the Vendor Identification String</h2>
<p>When CPUID executes with EAX set to 0, the processor returns the highest value the CPUID recognizes for returning basic processor information. The value is returned in the EAX register and is processor specific.</p>
<p>A vendor identification string is also returned in EBX, EDX, and ECX. For Intel processors, the string is “Genuin-eIntel” and is expressed:</p>
<p>EBX ← 756e6547h (* “Genu”, with G in the low eight bits of BL *)</p>
<p>EDX ← 49656e69h (* “ineI”, with i in the low eight bits of DL *)</p>
<p>ECX ← 6c65746eh (* “ntel”, with n in the low eight bits of CL *)</p>
<h2>INPUT EAX = 80000000H: Returns CPUID’s Highest Value for Extended Processor Information</h2>
<p>When CPUID executes with EAX set to 80000000H, the processor returns the highest value the processor recog-nizes for returning extended processor information. The value is returned in the EAX register and is processor specific.</p>
<h2>IA32_BIOS_SIGN_ID Returns Microcode Update Signature</h2>
<p>For processors that support the microcode update facility, the IA32_BIOS_SIGN_ID MSR is loaded with the update signature whenever CPUID executes. The signature is returned in the upper DWORD. For details, see Chapter 9 in the <em>Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A</em>.</p>
<h2>INPUT EAX = 01H: Returns Model, Family, Stepping Information</h2>
<p>When CPUID executes with EAX set to 01H, version information is returned in EAX (see Figure 3-6). For example: model, family, and processor type for the Intel Xeon processor 5100 series is as follows:</p>
<p>See Table 3-9 for available processor type values. Stepping IDs are provided as needed.</p>
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<h3>Figure 3-6.  Version Information Returned by CPUID in EAX</h3>
<h3>Table 3-9.  Processor Type Field</h3>
<table>
<tr>
<th>Type</th>
<th>Encoding</th></tr>
<tr>
<td>Original OEM Processor</td>
<td>00B</td></tr>
<tr>
<td>Intel OverDrive<sup>®</sup> Processor</td>
<td>01B</td></tr>
<tr>
<td>Dual processor (not applicable to Intel486 processors)</td>
<td>10B</td></tr>
<tr>
<td>Intel reserved</td>
<td>11B</td></tr></table>
<h3>NOTE</h3>
<p>See Chapter 19 in the <em>Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1</em>, for information on identifying earlier IA-32 processors.</p>
<p>The Extended Family ID needs to be examined only when the Family ID is 0FH. Integrate the fields into a display using the following rule:</p>
<p>IF Family_ID ≠ 0FH</p>
<p>THEN DisplayFamily = Family_ID;</p>
<p>ELSE DisplayFamily = Extended_Family_ID + Family_ID;</p>
<p>(* Right justify and zero-extend 4-bit field. *)</p>
<p>FI;</p>
<p>(* Show DisplayFamily as HEX field. *)</p>
<p>The Extended Model ID needs to be examined only when the Family ID is 06H or 0FH. Integrate the field into a display using the following rule:</p>
<p>IF (Family_ID = 06H or Family_ID = 0FH)</p>
<p>THEN DisplayModel = (Extended_Model_ID « 4) + Model_ID;</p>
<p>(* Right justify and zero-extend 4-bit field; display Model_ID as HEX field.*)</p>
<p>ELSE DisplayModel = Model_ID;</p>
<p>FI;</p>
<p>(* Show DisplayModel as HEX field. *)</p>
<h2>INPUT EAX = 01H: Returns Additional Information in EBX</h2>
<p>When CPUID executes with EAX set to 01H, additional information is returned to the EBX register:</p>
<h2>INPUT EAX = 01H: Returns Feature Information in ECX and EDX</h2>
<p>When CPUID executes with EAX set to 01H, feature information is returned in ECX and EDX.</p>
<p>For all feature flags, a 1 indicates that the feature is supported. Use Intel to properly interpret feature flags.</p>
<h3>NOTE</h3>
<p>Software must confirm that a processor feature is present using feature flags returned by CPUID prior to using the feature. Software should not depend on future offerings retaining all features.</p>
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<h3>Figure 3-7.  Feature Information Returned in the ECX Register</h3>
<h3>Table 3-10.  Feature Information Returned in the ECX Register</h3>
<p><strong>Bit #</strong></p>
<p><strong>Mnemonic</strong></p>
<p><strong>Description</strong></p>
<p><strong>Streaming SIMD Extensions 3 (SSE3). A value of 1 indicates the processor supports this</strong></p>
<p>0</p>
<p>SSE3</p>
<p>technology.</p>
<p><strong>PCLMULQDQ. A value of 1 indicates the processor supports the PCLMULQDQ instruction.</strong></p>
<p>1</p>
<p>PCLMULQDQ</p>
<p><strong>64-bit DS Area. A value of 1 indicates the processor supports DS area using 64-bit layout.</strong></p>
<p>2</p>
<p>DTES64</p>
<p><strong>MONITOR/MWAIT. A value of 1 indicates the processor supports this feature.</strong></p>
<p>3</p>
<p>MONITOR</p>
<p><strong>CPL Qualified Debug Store. A value of 1 indicates the processor supports the extensions to the</strong></p>
<p>4</p>
<p>DS-CPL</p>
<p>Debug Store feature to allow for branch message storage qualified by CPL.</p>
<p><strong>Virtual Machine Extensions. A value of 1 indicates that the processor supports this technology.</strong></p>
<p>5</p>
<p>VMX</p>
<p><strong>Safer Mode Extensions. A value of 1 indicates that the processor supports this technology. See</strong></p>
<p>6</p>
<p>SMX</p>
<p>Chapter 6, “Safer Mode Extensions Reference”.</p>
<p><strong>Enhanced Intel SpeedStep® technology. A value of 1 indicates that the processor supports this</strong></p>
<p>7</p>
<p>EIST</p>
<p>technology.</p>
<p><strong>Thermal Monitor 2. A value of 1 indicates whether the processor supports this technology.</strong></p>
<p>8</p>
<p>TM2</p>
<p>9</p>
<p>SSSE3</p>
<p>A value of 1 indicates the presence of the Supplemental Streaming SIMD Extensions 3 (SSSE3). A value of 0 indicates the instruction extensions are not present in the processor.</p>
<h3>Table 3-10.  Feature Information Returned in the ECX Register  (Contd.)</h3>
<p><strong>Bit #</strong></p>
<p><strong>Mnemonic</strong></p>
<p><strong>Description</strong></p>
<p><strong>L1 Context ID. A value of 1 indicates the L1 data cache mode can be set to either adaptive mode</strong></p>
<p>10</p>
<p>CNXT-ID</p>
<p>or shared mode. A value of 0 indicates this feature is not supported. See definition of the IA32_MISC_ENABLE MSR Bit 24 (L1 Data Cache Context Mode) for details.</p>
<p>11</p>
<p>SDBG</p>
<p>A value of 1 indicates the processor supports IA32_DEBUG_INTERFACE MSR for silicon debug.</p>
<p>12</p>
<p>FMA</p>
<p>A value of 1 indicates the processor supports FMA extensions using YMM state.</p>
<p><strong>CMPXCHG16B Available. A value of 1 indicates that the feature is available. See the</strong></p>
<p>13</p>
<p>CMPXCHG16B</p>
<p>“CMPXCHG8B/CMPXCHG16B—Compare and Exchange Bytes” section in this chapter for a description.</p>
<p><strong>xTPR Update Control. A value of 1 indicates that the processor supports changing</strong></p>
<p>14</p>
<p>xTPR Update Control</p>
<p>IA32_MISC_ENABLE[bit 23].</p>
<p><strong>Perfmon and Debug Capability: A value of 1 indicates the processor supports the performance</strong></p>
<p>15</p>
<p>PDCM</p>
<p>and debug feature indication MSR IA32_PERF_CAPABILITIES.</p>
<p>16</p>
<p>Reserved</p>
<p>Reserved</p>
<p><strong>Process-context identifiers. A value of 1 indicates that the processor supports PCIDs and that</strong></p>
<p>17</p>
<p>PCID</p>
<p>software may set CR4.PCIDE to 1.</p>
<p>18</p>
<p>DCA</p>
<p> A value of 1 indicates the processor supports the ability to prefetch data from a memory mapped device.</p>
<p>19</p>
<p>SSE4.1</p>
<p>A value of 1 indicates that the processor supports SSE4.1.</p>
<p>20</p>
<p>SSE4.2</p>
<p>A value of 1 indicates that the processor supports SSE4.2.</p>
<p>21</p>
<p>x2APIC</p>
<p>A value of 1 indicates that the processor supports x2APIC feature.</p>
<p>22</p>
<p>MOVBE</p>
<p>A value of 1 indicates that the processor supports MOVBE instruction.</p>
<p>23</p>
<p>POPCNT</p>
<p>A value of 1 indicates that the processor supports the POPCNT instruction.</p>
<p>24</p>
<p>TSC-Deadline</p>
<p>A value of 1 indicates that the processor’s local APIC timer supports one-shot operation using a TSC deadline value.</p>
<p>25</p>
<p>AESNI</p>
<p>A value of 1 indicates that the processor supports the AESNI instruction extensions.</p>
<p>26</p>
<p>XSAVE</p>
<p>A value of 1 indicates that the processor supports the XSAVE/XRSTOR processor extended states feature, the XSETBV/XGETBV instructions, and XCR0.</p>
<p>27</p>
<p>OSXSAVE</p>
<p>A value of 1 indicates that the OS has set CR4.OSXSAVE[bit 18] to enable XSETBV/XGETBV instructions to access XCR0 and to support processor extended state management using XSAVE/XRSTOR.</p>
<p>28</p>
<p>AVX</p>
<p>A value of 1 indicates the processor supports the AVX instruction extensions.</p>
<p>29</p>
<p>F16C</p>
<p>A value of 1 indicates that processor supports 16-bit floating-point conversion instructions.</p>
<p>30</p>
<p>RDRAND</p>
<p>A value of 1 indicates that processor supports RDRAND instruction.</p>
<p>31</p>
<p>Not Used</p>
<p>Always returns 0.</p>
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<text y="149863.306888" x="119.46" style="font-size:7.991000pt" lengthAdjust="spacingAndGlyphs" textLength="73.3701656">PBE–Pend. Brk. EN.</text>
<text y="149872.306888" x="119.46" style="font-size:7.991000pt" lengthAdjust="spacingAndGlyphs" textLength="70.3999109">TM–Therm. Monitor</text>
<text y="149881.247188" x="119.46" style="font-size:7.991000pt" lengthAdjust="spacingAndGlyphs" textLength="73.1863726">HTT–Multi-threading</text>
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<text y="149899.247788" x="119.46" style="font-size:7.991000pt" lengthAdjust="spacingAndGlyphs" textLength="86.8605718">SSE2–SSE2 Extensions</text>
<text y="149908.247988" x="119.46" style="font-size:7.991000pt" lengthAdjust="spacingAndGlyphs" textLength="77.8579112">SSE–SSE Extensions</text>
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<text y="149953.189388" x="119.46" style="font-size:7.991000pt" lengthAdjust="spacingAndGlyphs" textLength="106.1092926">CLFSH–CLFLUSH instruction</text>
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<text y="150088.253288" x="119.46" style="font-size:7.991000pt" lengthAdjust="spacingAndGlyphs" textLength="98.553003">PSE–Page Size Extensions</text>
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<text y="150115.193288" x="119.46" style="font-size:7.991000pt" lengthAdjust="spacingAndGlyphs" textLength="81.4610531">FPU–x87 FPU on Chip</text>
<text y="150134.812788" x="139.7396" style="font-size:7.991000pt" lengthAdjust="spacingAndGlyphs" textLength="34.4364154">Reserved</text>
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<h3>Figure 3-8.  Feature Information Returned in the EDX Register</h3>
<h3>Table 3-11.  More on Feature Information Returned in the EDX Register</h3>
<table>
<tr>
<th>Bit #</th>
<th>Mnemonic</th>
<th>Description</th></tr>
<tr>
<td>0</td>
<td>FPU</td>
<th>Floating Point Unit On-Chip. The processor contains an x87 FPU.</th></tr>
<tr>
<td>1</td>
<td>VME</td>
<th>Virtual 8086 Mode Enhancements. Virtual 8086 mode enhancements, including CR4.VME for controlling the feature, CR4.PVI for protected mode virtual interrupts, software interrupt indirection, expansion of the TSS with the software indirection bitmap, and EFLAGS.VIF and EFLAGS.VIP flags.</th></tr>
<tr>
<td>2</td>
<td>DE</td>
<th>Debugging Extensions. Support for I/O breakpoints, including CR4.DE for controlling the feature, and optional trapping of accesses to DR4 and DR5.</th></tr>
<tr>
<td>3</td>
<td>PSE</td>
<th>Page Size Extension. Large pages of size 4 MByte are supported, including CR4.PSE for controlling the feature, the defined dirty bit in PDE (Page Directory Entries), optional reserved bit trapping in CR3, PDEs, and PTEs.</th></tr>
<tr>
<td>4</td>
<td>TSC</td>
<th>Time Stamp Counter. The RDTSC instruction is supported, including CR4.TSD for controlling privilege.</th></tr>
<tr>
<td>5</td>
<td>MSR</td>
<th>Model Specific Registers RDMSR and WRMSR Instructions. The RDMSR and WRMSR instructions are supported. Some of the MSRs are implementation dependent.</th></tr>
<tr>
<td>6</td>
<td>PAE</td>
<th>Physical Address Extension. Physical addresses greater than 32 bits are supported: extended page table entry formats, an extra level in the page translation tables is defined, 2-MByte pages are supported instead of 4 Mbyte pages if PAE bit is 1.</th></tr>
<tr>
<td>7</td>
<td>MCE</td>
<th>Machine Check Exception. Exception 18 is defined for Machine Checks, including CR4.MCE for controlling the feature. This feature does not define the model-specific implementations of machine-check error logging, reporting, and processor shutdowns. Machine Check exception handlers may have to depend on processor version to do model specific processing of the exception, or test for the presence of the Machine Check feature.</th></tr>
<tr>
<td>8</td>
<td>CX8</td>
<th>CMPXCHG8B Instruction. The compare-and-exchange 8 bytes (64 bits) instruction is supported (implicitly locked and atomic).</th></tr>
<tr>
<td>9</td>
<td>APIC</td>
<th>APIC On-Chip. The processor contains an Advanced Programmable Interrupt Controller (APIC), responding to memory mapped commands in the physical address range FFFE0000H to FFFE0FFFH (by default - some processors permit the APIC to be relocated).</th></tr>
<tr>
<td>10</td>
<td>Reserved</td>
<td>Reserved</td></tr>
<tr>
<td>11</td>
<td>SEP</td>
<th>SYSENTER and SYSEXIT Instructions. The SYSENTER and SYSEXIT and associated MSRs are supported.</th></tr>
<tr>
<td>12</td>
<td>MTRR</td>
<th>Memory Type Range Registers. MTRRs are supported. The MTRRcap MSR contains feature bits that describe what memory types are supported, how many variable MTRRs are supported, and whether fixed MTRRs are supported.</th></tr>
<tr>
<td>13</td>
<td>PGE</td>
<th>Page Global Bit. The global bit is supported in paging-structure entries that map a page, indicating TLB entries that are common to different processes and need not be flushed. The CR4.PGE bit controls this feature.</th></tr>
<tr>
<td>14</td>
<td>MCA</td>
<th>Machine Check Architecture. A value of 1 indicates the Machine Check Architecture of reporting machine errors is supported. The MCG_CAP MSR contains feature bits describing how many banks of error reporting MSRs are supported.</th></tr>
<tr>
<td>15</td>
<td>CMOV</td>
<th>Conditional Move Instructions. The conditional move instruction CMOV is supported. In addition, if x87 FPU is present as indicated by the CPUID.FPU feature bit, then the FCOMI and FCMOV instructions are supported</th></tr>
<tr>
<td>16</td>
<td>PAT</td>
<th>Page Attribute Table. Page Attribute Table is supported. This feature augments the Memory Type Range Registers (MTRRs), allowing an operating system to specify attributes of memory accessed through a linear address on a 4KB granularity.</th></tr>
<tr>
<td>17</td>
<td>PSE-36</td>
<th>36-Bit Page Size Extension. 4-MByte pages addressing physical memory beyond 4 GBytes are supported with 32-bit paging. This feature indicates that upper bits of the physical address of a 4-MByte page are encoded in bits 20:13 of the page-directory entry. Such physical addresses are limited by MAXPHYADDR and may be up to 40 bits in size.</th></tr>
<tr>
<td>18</td>
<td>PSN</td>
<th>Processor Serial Number. The processor supports the 96-bit processor identification number feature and the feature is enabled.</th></tr>
<tr>
<td>19</td>
<td>CLFSH</td>
<th>CLFLUSH Instruction. CLFLUSH Instruction is supported.</th></tr>
<tr>
<td>20</td>
<td>Reserved</td>
<td>Reserved</td></tr></table>
<h3>Table 3-11.  More on Feature Information Returned in the EDX Register (Contd.)</h3>
<table>
<tr>
<th>Bit #</th>
<th>Mnemonic</th>
<th>Description</th></tr>
<tr>
<td>21</td>
<td>DS</td>
<th>Debug Store. The processor supports the ability to write debug information into a memory resident buffer. This feature is used by the branch trace store (BTS) and precise event-based sampling (PEBS) facilities (see Chapter 23, “Introduction to Virtual-Machine Extensions,” in the <em>Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3C</em>).</th></tr>
<tr>
<td>22</td>
<td>ACPI</td>
<th>Thermal Monitor and Software Controlled Clock Facilities. The processor implements internal MSRs that allow processor temperature to be monitored and processor performance to be modulated in predefined duty cycles under software control.</th></tr>
<tr>
<td>23</td>
<td>MMX</td>
<th>Intel MMX Technology. The processor supports the Intel MMX technology.</th></tr>
<tr>
<td>24</td>
<td>FXSR</td>
<th>FXSAVE and FXRSTOR Instructions. The FXSAVE and FXRSTOR instructions are supported for fast save and restore of the floating point context. Presence of this bit also indicates that CR4.OSFXSR is available for an operating system to indicate that it supports the FXSAVE and FXRSTOR instructions.</th></tr>
<tr>
<td>25</td>
<td>SSE</td>
<th>SSE. The processor supports the SSE extensions.</th></tr>
<tr>
<td>26</td>
<td>SSE2</td>
<th>SSE2. The processor supports the SSE2 extensions.</th></tr>
<tr>
<td>27</td>
<td>SS</td>
<th>Self Snoop. The processor supports the management of conflicting memory types by performing a snoop of its own cache structure for transactions issued to the bus.</th></tr>
<tr>
<td>28</td>
<td>HTT</td>
<th>Max APIC IDs reserved field is Valid. A value of 0 for HTT indicates there is only a single logical processor in the package and software should assume only a single APIC ID is reserved. A value of 1 for HTT indicates the value in CPUID.1.EBX[23:16] (the Maximum number of addressable IDs for logical processors in this package) is valid for the package.</th></tr>
<tr>
<td>29</td>
<td>TM</td>
<th>Thermal Monitor. The processor implements the thermal monitor automatic thermal control circuitry (TCC).</th></tr>
<tr>
<td>30</td>
<td>Reserved</td>
<td>Reserved</td></tr>
<tr>
<td>31</td>
<td>PBE</td>
<th>Pending Break Enable. The processor supports the use of the FERR#/PBE# pin when the processor is in the stop-clock state (STPCLK# is asserted) to signal the processor that an interrupt is pending and that the processor should return to normal operation to handle the interrupt. Bit 10 (PBE enable) in the IA32_MISC_ENABLE MSR enables this capability.</th></tr></table>
<h2>INPUT EAX = 02H: TLB/Cache/Prefetch Information Returned in EAX, EBX, ECX, EDX</h2>
<p>When CPUID executes with EAX set to 02H, the processor returns information about the processor’s internal TLBs, cache and prefetch hardware in the EAX, EBX, ECX, and EDX registers. The information is reported in encoded form and fall into the following categories:</p>
<h3>Table 3-12.  Encoding of CPUID Leaf 2 Descriptors</h3>
<table>
<tr>
<th> Value</th>
<th>Type</th>
<th>Description</th></tr>
<tr>
<td>00H</td>
<td>General</td>
<td>Null descriptor, this byte contains no information</td></tr>
<tr>
<td>01H</td>
<td>TLB</td>
<td>Instruction TLB: 4 KByte pages, 4-way set associative, 32 entries</td></tr>
<tr>
<td>02H</td>
<td>TLB</td>
<td>Instruction TLB: 4 MByte pages, fully associative, 2 entries</td></tr>
<tr>
<td>03H</td>
<td>TLB</td>
<td>Data TLB: 4 KByte pages, 4-way set associative, 64 entries</td></tr>
<tr>
<td>04H</td>
<td>TLB</td>
<td>Data TLB: 4 MByte pages, 4-way set associative, 8 entries</td></tr>
<tr>
<td>05H</td>
<td>TLB</td>
<td>Data TLB1: 4 MByte pages, 4-way set associative, 32 entries</td></tr>
<tr>
<td>06H</td>
<td>Cache</td>
<td>1st-level instruction cache: 8 KBytes, 4-way set associative, 32 byte line size</td></tr>
<tr>
<td>08H</td>
<td>Cache</td>
<td>1st-level instruction cache: 16 KBytes, 4-way set associative, 32 byte line size</td></tr>
<tr>
<td>09H</td>
<td>Cache</td>
<td>1st-level instruction cache: 32KBytes, 4-way set associative, 64 byte line size</td></tr>
<tr>
<td>0AH</td>
<td>Cache</td>
<td>1st-level data cache: 8 KBytes, 2-way set associative, 32 byte line size</td></tr>
<tr>
<td>0BH</td>
<td>TLB</td>
<td>Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries</td></tr>
<tr>
<td>0CH</td>
<td>Cache</td>
<td>1st-level data cache: 16 KBytes, 4-way set associative, 32 byte line size</td></tr>
<tr>
<td>0DH</td>
<td>Cache</td>
<td>1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size</td></tr>
<tr>
<td>0EH</td>
<td>Cache</td>
<td>1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size</td></tr>
<tr>
<td>1DH</td>
<td>Cache</td>
<td>2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size</td></tr>
<tr>
<td>21H</td>
<td>Cache</td>
<td>2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size</td></tr>
<tr>
<td>22H</td>
<td>Cache</td>
<td>3rd-level cache: 512 KBytes, 4-way set associative, 64 byte line size, 2 lines per sector</td></tr>
<tr>
<td>23H</td>
<td>Cache</td>
<td>3rd-level cache: 1 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector</td></tr>
<tr>
<td>24H</td>
<td>Cache</td>
<td>2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size</td></tr>
<tr>
<td>25H</td>
<td>Cache</td>
<td>3rd-level cache: 2 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector</td></tr>
<tr>
<td>29H</td>
<td>Cache</td>
<td>3rd-level cache: 4 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector</td></tr>
<tr>
<td>2CH</td>
<td>Cache</td>
<td>1st-level data cache: 32 KBytes, 8-way set associative, 64 byte line size</td></tr>
<tr>
<td>30H</td>
<td>Cache</td>
<td>1st-level instruction cache: 32 KBytes, 8-way set associative, 64 byte line size</td></tr>
<tr>
<td>40H</td>
<td>Cache</td>
<td>No 2nd-level cache or, if processor contains a valid 2nd-level cache, no 3rd-level cache</td></tr>
<tr>
<td>41H</td>
<td>Cache</td>
<td>2nd-level cache: 128 KBytes, 4-way set associative, 32 byte line size</td></tr>
<tr>
<td>42H</td>
<td>Cache</td>
<td>2nd-level cache: 256 KBytes, 4-way set associative, 32 byte line size</td></tr>
<tr>
<td>43H</td>
<td>Cache</td>
<td>2nd-level cache: 512 KBytes, 4-way set associative, 32 byte line size</td></tr>
<tr>
<td>44H</td>
<td>Cache</td>
<td>2nd-level cache: 1 MByte, 4-way set associative, 32 byte line size</td></tr>
<tr>
<td>45H</td>
<td>Cache</td>
<td>2nd-level cache: 2 MByte, 4-way set associative, 32 byte line size</td></tr>
<tr>
<td>46H</td>
<td>Cache</td>
<td>3rd-level cache: 4 MByte, 4-way set associative, 64 byte line size</td></tr>
<tr>
<td>47H</td>
<td>Cache</td>
<td>3rd-level cache: 8 MByte, 8-way set associative, 64 byte line size</td></tr>
<tr>
<td>48H</td>
<td>Cache</td>
<td>2nd-level cache: 3MByte, 12-way set associative, 64 byte line size</td></tr>
<tr>
<td>49H</td>
<td>Cache</td>
<td>
<p>3rd-level cache: 4MB, 16-way set associative, 64-byte line size (Intel Xeon processor MP, Family 0FH, Model 06H);</p>
<p>2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size</p></td></tr>
<tr>
<td>4AH</td>
<td>Cache</td>
<td>3rd-level cache: 6MByte, 12-way set associative, 64 byte line size</td></tr>
<tr>
<td>4BH</td>
<td>Cache</td>
<td>3rd-level cache: 8MByte, 16-way set associative, 64 byte line size</td></tr>
<tr>
<td>4CH</td>
<td>Cache</td>
<td>3rd-level cache: 12MByte, 12-way set associative, 64 byte line size</td></tr>
<tr>
<td>4DH</td>
<td>Cache</td>
<td>3rd-level cache: 16MByte, 16-way set associative, 64 byte line size</td></tr>
<tr>
<td>4EH</td>
<td>Cache</td>
<td>2nd-level cache: 6MByte, 24-way set associative, 64 byte line size</td></tr>
<tr>
<td>4FH</td>
<td>TLB</td>
<td>Instruction TLB: 4 KByte pages, 32 entries</td></tr></table>
<h3>Table 3-12.  Encoding of CPUID Leaf 2 Descriptors  (Contd.)</h3>
<table>
<tr>
<th> Value</th>
<th>Type</th>
<th>Description</th></tr>
<tr>
<td>50H</td>
<td>TLB</td>
<td>Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 64 entries</td></tr>
<tr>
<td>51H</td>
<td>TLB</td>
<td>Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 128 entries</td></tr>
<tr>
<td>52H</td>
<td>TLB</td>
<td>Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 256 entries</td></tr>
<tr>
<td>55H</td>
<td>TLB</td>
<td>Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries</td></tr>
<tr>
<td>56H</td>
<td>TLB</td>
<td>Data TLB0: 4 MByte pages, 4-way set associative, 16 entries</td></tr>
<tr>
<td>57H</td>
<td>TLB</td>
<td>Data TLB0: 4 KByte pages, 4-way associative, 16 entries</td></tr>
<tr>
<td>59H</td>
<td>TLB</td>
<td>Data TLB0: 4 KByte pages, fully associative, 16 entries</td></tr>
<tr>
<td>5AH</td>
<td>TLB</td>
<td>Data TLB0: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries</td></tr>
<tr>
<td>5BH</td>
<td>TLB</td>
<td>Data TLB: 4 KByte and 4 MByte pages, 64 entries</td></tr>
<tr>
<td>5CH</td>
<td>TLB</td>
<td>Data TLB: 4 KByte and 4 MByte pages,128 entries</td></tr>
<tr>
<td>5DH</td>
<td>TLB</td>
<td>Data TLB: 4 KByte and 4 MByte pages,256 entries</td></tr>
<tr>
<td>60H</td>
<td>Cache</td>
<td>1st-level data cache: 16 KByte, 8-way set associative, 64 byte line size</td></tr>
<tr>
<td>61H</td>
<td>TLB</td>
<td>Instruction TLB: 4 KByte pages, fully associative, 48 entries</td></tr>
<tr>
<td>63H</td>
<td>TLB</td>
<td>Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries</td></tr>
<tr>
<td>64H</td>
<td>TLB</td>
<td>Data TLB: 4 KByte pages, 4-way set associative, 512 entries</td></tr>
<tr>
<td>66H</td>
<td>Cache</td>
<td>1st-level data cache: 8 KByte, 4-way set associative, 64 byte line size</td></tr>
<tr>
<td>67H</td>
<td>Cache</td>
<td>1st-level data cache: 16 KByte, 4-way set associative, 64 byte line size</td></tr>
<tr>
<td>68H</td>
<td>Cache</td>
<td>1st-level data cache: 32 KByte, 4-way set associative, 64 byte line size</td></tr>
<tr>
<td>6AH</td>
<td>Cache</td>
<td>uTLB: 4 KByte pages, 8-way set associative, 64 entries</td></tr>
<tr>
<td>6BH</td>
<td>Cache</td>
<td>DTLB: 4 KByte pages, 8-way set associative, 256 entries</td></tr>
<tr>
<td>6CH</td>
<td>Cache</td>
<td>DTLB: 2M/4M pages, 8-way set associative, 128 entries</td></tr>
<tr>
<td>6DH</td>
<td>Cache</td>
<td>DTLB: 1 GByte pages, fully associative, 16 entries</td></tr>
<tr>
<td>70H</td>
<td>Cache</td>
<td>Trace cache: 12 K-µop, 8-way set associative</td></tr>
<tr>
<td>71H</td>
<td>Cache</td>
<td>Trace cache: 16 K-µop, 8-way set associative</td></tr>
<tr>
<td>72H</td>
<td>Cache</td>
<td>Trace cache: 32 K-µop, 8-way set associative</td></tr>
<tr>
<td>76H</td>
<td>TLB</td>
<td>Instruction TLB: 2M/4M pages, fully associative, 8 entries</td></tr>
<tr>
<td>78H</td>
<td>Cache</td>
<td>2nd-level cache: 1 MByte, 4-way set associative, 64byte line size</td></tr>
<tr>
<td>79H</td>
<td>Cache</td>
<td>2nd-level cache: 128 KByte, 8-way set associative, 64 byte line size, 2 lines per sector</td></tr>
<tr>
<td>7AH</td>
<td>Cache</td>
<td>2nd-level cache: 256 KByte, 8-way set associative, 64 byte line size, 2 lines per sector</td></tr>
<tr>
<td>7BH</td>
<td>Cache</td>
<td>2nd-level cache: 512 KByte, 8-way set associative, 64 byte line size, 2 lines per sector</td></tr>
<tr>
<td>7CH</td>
<td>Cache</td>
<td>2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size, 2 lines per sector</td></tr>
<tr>
<td>7DH</td>
<td>Cache</td>
<td>2nd-level cache: 2 MByte, 8-way set associative, 64byte line size</td></tr>
<tr>
<td>7FH</td>
<td>Cache</td>
<td>2nd-level cache: 512 KByte, 2-way set associative, 64-byte line size</td></tr>
<tr>
<td>80H</td>
<td>Cache</td>
<td>2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size</td></tr>
<tr>
<td>82H</td>
<td>Cache</td>
<td>2nd-level cache: 256 KByte, 8-way set associative, 32 byte line size</td></tr>
<tr>
<td>83H</td>
<td>Cache</td>
<td>2nd-level cache: 512 KByte, 8-way set associative, 32 byte line size</td></tr>
<tr>
<td>84H</td>
<td>Cache</td>
<td>2nd-level cache: 1 MByte, 8-way set associative, 32 byte line size</td></tr>
<tr>
<td>85H</td>
<td>Cache</td>
<td>2nd-level cache: 2 MByte, 8-way set associative, 32 byte line size</td></tr>
<tr>
<td>86H</td>
<td>Cache</td>
<td>2nd-level cache: 512 KByte, 4-way set associative, 64 byte line size</td></tr>
<tr>
<td>87H</td>
<td>Cache</td>
<td>2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size</td></tr></table>
<h3>Table 3-12.  Encoding of CPUID Leaf 2 Descriptors  (Contd.)</h3>
<table>
<tr>
<th> Value</th>
<th>Type</th>
<th>Description</th></tr>
<tr>
<td>A0H</td>
<td>DTLB</td>
<td>DTLB: 4k pages, fully associative, 32 entries</td></tr>
<tr>
<td>B0H</td>
<td>TLB</td>
<td>Instruction TLB: 4 KByte pages, 4-way set associative, 128 entries</td></tr>
<tr>
<td>B1H</td>
<td>TLB</td>
<td>Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries</td></tr>
<tr>
<td>B2H</td>
<td>TLB</td>
<td>Instruction TLB: 4KByte pages, 4-way set associative, 64 entries</td></tr>
<tr>
<td>B3H</td>
<td>TLB</td>
<td>Data TLB: 4 KByte pages, 4-way set associative, 128 entries</td></tr>
<tr>
<td>B4H</td>
<td>TLB</td>
<td>Data TLB1: 4 KByte pages, 4-way associative, 256 entries</td></tr>
<tr>
<td>B5H</td>
<td>TLB</td>
<td>Instruction TLB: 4KByte pages, 8-way set associative, 64 entries</td></tr>
<tr>
<td>B6H</td>
<td>TLB</td>
<td>Instruction TLB: 4KByte pages, 8-way set associative, 128 entries</td></tr>
<tr>
<td>BAH</td>
<td>TLB</td>
<td>Data TLB1: 4 KByte pages, 4-way associative, 64 entries</td></tr>
<tr>
<td>C0H</td>
<td>TLB</td>
<td>Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries</td></tr>
<tr>
<td>C1H</td>
<td>STLB</td>
<td>Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries</td></tr>
<tr>
<td>C2H</td>
<td>DTLB</td>
<td>DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries</td></tr>
<tr>
<td>C3H</td>
<td>STLB</td>
<td>Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries.</td></tr>
<tr>
<td>C4H</td>
<td>DTLB</td>
<td>DTLB: 2M/4M Byte pages, 4-way associative, 32 entries</td></tr>
<tr>
<td>CAH</td>
<td>STLB</td>
<td>Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries</td></tr>
<tr>
<td>D0H</td>
<td>Cache</td>
<td>3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size</td></tr>
<tr>
<td>D1H</td>
<td>Cache</td>
<td>3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size</td></tr>
<tr>
<td>D2H</td>
<td>Cache</td>
<td>3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size</td></tr>
<tr>
<td>D6H</td>
<td>Cache</td>
<td>3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size</td></tr>
<tr>
<td>D7H</td>
<td>Cache</td>
<td>3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size</td></tr>
<tr>
<td>D8H</td>
<td>Cache</td>
<td>3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size</td></tr>
<tr>
<td>DCH</td>
<td>Cache</td>
<td>3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size</td></tr>
<tr>
<td>DDH</td>
<td>Cache</td>
<td>3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size</td></tr>
<tr>
<td>DEH</td>
<td>Cache</td>
<td>3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size</td></tr>
<tr>
<td>E2H</td>
<td>Cache</td>
<td>3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size</td></tr>
<tr>
<td>E3H</td>
<td>Cache</td>
<td>3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size</td></tr>
<tr>
<td>E4H</td>
<td>Cache</td>
<td>3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size</td></tr>
<tr>
<td>EAH</td>
<td>Cache</td>
<td>3rd-level cache: 12MByte, 24-way set associative, 64 byte line size</td></tr>
<tr>
<td>EBH</td>
<td>Cache</td>
<td>3rd-level cache: 18MByte, 24-way set associative, 64 byte line size</td></tr>
<tr>
<td>ECH</td>
<td>Cache</td>
<td>3rd-level cache: 24MByte, 24-way set associative, 64 byte line size</td></tr>
<tr>
<td>F0H</td>
<td>Prefetch</td>
<td>64-Byte prefetching</td></tr>
<tr>
<td>F1H</td>
<td>Prefetch</td>
<td>128-Byte prefetching</td></tr>
<tr>
<td>FFH</td>
<td>General</td>
<td>CPUID leaf 2 does not report cache descriptor information, use CPUID leaf 4 to query cache parameters</td></tr></table>
<h2>Example 3-1.  Example of Cache and TLB Interpretation</h2>
<p>The first member of the family of Pentium 4 processors returns the following information about caches and TLBs when the CPUID executes with an input value of 2:</p>
<p>EAX</p>
<p>66 5B 50 01H</p>
<p>EBX</p>
<p>0H</p>
<p>ECX</p>
<p>0H</p>
<p>EDX</p>
<p>00 7A 70 00H</p>
<p>Which means:</p>
<p>— 50H - a 64-entry instruction TLB, for mapping 4-KByte and 2-MByte or 4-MByte pages.</p>
<p>— 5BH - a 64-entry data TLB, for mapping 4-KByte and 4-MByte pages.</p>
<p>— 66H - an 8-KByte 1st level data cache, 4-way set associative, with a 64-Byte cache line size.</p>
<p>— 00H - NULL descriptor.</p>
<p>— 70H - Trace cache: 12 K-µop, 8-way set associative.</p>
<p>— 7AH - a 256-KByte 2nd level cache, 8-way set associative, with a sectored, 64-byte cache line size.</p>
<p>— 00H - NULL descriptor.</p>
<h2>INPUT EAX = 04H: Returns Deterministic Cache Parameters for Each Level</h2>
<p>When CPUID executes with EAX set to 04H and ECX contains an index value, the processor returns encoded data that describe a set of deterministic cache parameters (for the cache level associated with the input in ECX). Valid index values start from 0.</p>
<p>Software can enumerate the deterministic cache parameters for each level of the cache hierarchy starting with an index value of 0, until the parameters report the value associated with the cache type field is 0. The architecturally defined fields reported by deterministic cache parameters are documented in Table 3-8.</p>
<p>This Cache Size in Bytes</p>
<p>= (Ways + 1) * (Partitions + 1) * (Line_Size + 1) * (Sets + 1)</p>
<p>= (EBX[31:22] + 1) * (EBX[21:12] + 1) * (EBX[11:0] + 1) * (ECX + 1)</p>
<p>The CPUID leaf 04H also reports data that can be used to derive the topology of processor cores in a physical package. This information is constant for all valid index values. Software can query the raw data reported by executing CPUID with EAX=04H and ECX=0 and use it as part of the topology enumeration algorithm described in Chapter 8, “Multiple-Processor Management,” in the <em>Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A</em>.</p>
<h2>INPUT EAX = 05H: Returns MONITOR and MWAIT Features</h2>
<p>When CPUID executes with EAX set to 05H, the processor returns information about features available to MONITOR/MWAIT instructions. The MONITOR instruction is used for address-range monitoring in conjunction with MWAIT instruction. The MWAIT instruction optionally provides additional extensions for advanced power manage-ment. See Table 3-8.</p>
<h2>INPUT EAX = 06H: Returns Thermal and Power Management Features</h2>
<p>When CPUID executes with EAX set to 06H, the processor returns information about thermal and power manage-ment features. See Table 3-8.</p>
<h2>INPUT EAX = 07H: Returns Structured Extended Feature Enumeration Information</h2>
<p>When CPUID executes with EAX set to 07H and ECX = 0, the processor returns information about the maximum input value for sub-leaves that contain extended feature flags. See Table 3-8.</p>
<h2>When CPUID executes with EAX set to 07H and the input value of ECX is invalid (see leaf 07H entry in Table 3-8), the processor returns 0 in EAX/EBX/ECX/EDX. In subleaf 0, EAX returns the maximum input value of the highest</h2>
<h2>leaf 7 sub-leaf, and EBX, ECX &amp; EDX contain information of extended feature flags.</h2>
<h2>INPUT EAX = 09H: Returns Direct Cache Access Information</h2>
<p>When CPUID executes with EAX set to 09H, the processor returns information about Direct Cache Access capabili-ties. See Table 3-8.</p>
<h2>INPUT EAX = 0AH: Returns Architectural Performance Monitoring Features</h2>
<p>When CPUID executes with EAX set to 0AH, the processor returns information about support for architectural performance monitoring capabilities. Architectural performance monitoring is supported if the version ID (see Table 3-8) is greater than Pn 0. See Table 3-8.</p>
<p>For each version of architectural performance monitoring capability, software must enumerate this leaf to discover the programming facilities and the architectural performance events available in the processor. The details are described in Chapter 23, “Introduction to Virtual-Machine Extensions,” in the <em>Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3C</em>.</p>
<h2>INPUT EAX = 0BH: Returns Extended Topology Information</h2>
<p>When CPUID executes with EAX set to 0BH, the processor returns information about extended topology enumera-tion data. Software must detect the presence of CPUID leaf 0BH by verifying (a) the highest leaf index supported by CPUID is &gt;= 0BH, and (b) CPUID.0BH:EBX[15:0] reports a non-zero value. See Table 3-8.</p>
<h2>INPUT EAX = 0DH: Returns Processor Extended States Enumeration Information</h2>
<p>When CPUID executes with EAX set to 0DH and ECX = 0, the processor returns information about the bit-vector representation of all processor state extensions that are supported in the processor and storage size requirements of the XSAVE/XRSTOR area. See Table 3-8.</p>
<p>When CPUID executes with EAX set to 0DH and ECX = n (n &gt; 1, and is a valid sub-leaf index), the processor returns information about the size and offset of each processor extended state save area within the XSAVE/XRSTOR area. See Table 3-8. Software can use the forward-extendable technique depicted below to query the valid sub-leaves and obtain size and offset information for each processor extended state save area:</p>
<p>For i = 2 to 62 // sub-leaf 1 is reserved</p>
<p>IF (CPUID.(EAX=0DH, ECX=0):VECTOR[i] = 1 ) // VECTOR is the 64-bit value of EDX:EAX</p>
<p>Execute CPUID.(EAX=0DH, ECX = i) to examine size and offset for sub-leaf i;</p>
<p>FI;</p>
<h2>INPUT EAX = 0FH: Returns Intel Resource Director Technology (Intel RDT) Monitoring Enumeration Information</h2>
<p>When CPUID executes with EAX set to 0FH and ECX = 0, the processor returns information about the bit-vector representation of QoS monitoring resource types that are supported in the processor and maximum range of RMID values the processor can use to monitor of any supported resource types. Each bit, starting from bit 1, corresponds to a specific resource type if the bit is set. The bit position corresponds to the sub-leaf index (or ResID) that soft-ware must use to query QoS monitoring capability available for that type. See Table 3-8.</p>
<p>When CPUID executes with EAX set to 0FH and ECX = n (n &gt;= 1, and is a valid ResID), the processor returns infor-mation software can use to program IA32_PQR_ASSOC, IA32_QM_EVTSEL MSRs before reading QoS data from the IA32_QM_CTR MSR.</p>
<h2>INPUT EAX = 10H: Returns Intel Resource Director Technology (Intel RDT) Allocation Enumeration Information</h2>
<p>When CPUID executes with EAX set to 10H and ECX = 0, the processor returns information about the bit-vector representation of QoS Enforcement resource types that are supported in the processor. Each bit, starting from bit 1, corresponds to a specific resource type if the bit is set. The bit position corresponds to the sub-leaf index (or ResID) that software must use to query QoS enforcement capability available for that type. See Table 3-8.</p>
<p>When CPUID executes with EAX set to 10H and ECX = n (n &gt;= 1, and is a valid ResID), the processor returns infor-mation about available classes of service and range of QoS mask MSRs that software can use to configure each class of services using capability bit masks in the QoS Mask registers, IA32_resourceType_Mask_n.</p>
<h2>INPUT EAX = 12H: Returns Intel SGX Enumeration Information</h2>
<p>When CPUID executes with EAX set to 12H and ECX = 0H, the processor returns information about Intel SGX capa-bilities. See Table 3-8.</p>
<p>When CPUID executes with EAX set to 12H and ECX = 1H, the processor returns information about Intel SGX attri-butes. See Table 3-8.</p>
<p>When CPUID executes with EAX set to 12H and ECX = n (n &gt; 1), the processor returns information about Intel SGX Enclave Page Cache. See Table 3-8.</p>
<h2>INPUT EAX = 14H: Returns Intel Processor Trace Enumeration Information</h2>
<p>When CPUID executes with EAX set to 14H and ECX = 0H, the processor returns information about Intel Processor Trace extensions. See Table 3-8.</p>
<p>When CPUID executes with EAX set to 14H and ECX = n (n &gt; 0 and less than the number of non-zero bits in CPUID.(EAX=14H, ECX= 0H).EAX), the processor returns information about packet generation in Intel Processor Trace. See Table 3-8.</p>
<h2>INPUT EAX = 15H: Returns Time Stamp Counter/Core Crystal Clock Information</h2>
<p>When CPUID executes with EAX set to 15H and ECX = 0H, the processor returns information about Time Stamp Counter/Core Crystal Clock. See Table 3-8.</p>
<h2>INPUT EAX = 16H: Returns Processor Frequency Information</h2>
<p>When CPUID executes with EAX set to 16H, the processor returns information about Processor Frequency Informa-tion. See Table 3-8.</p>
<h2>INPUT EAX = 17H: Returns System-On-Chip Information</h2>
<p>When CPUID executes with EAX set to 17H, the processor returns information about the System-On-Chip Vendor Attribute Enumeration. See Table 3-8.</p>
<h2>METHODS FOR RETURNING BRANDING INFORMATION</h2>
<p>Use the following techniques to access branding information:</p>
<p>1.</p>
<p>Processor brand string method.</p>
<p>2.</p>
<p>Processor brand index; this method uses a software supplied brand string table.</p>
<p>These two methods are discussed in the following sections. For methods that are available in early processors, see Section: “Identification of Earlier IA-32 Processors” in Chapter 19 of the <em>Intel® 64 and IA-32 Architectures Soft-ware Developer’s Manual, Volume 1</em>.</p>
<h2>The Processor Brand String Method</h2>
<p>Figure 3-9 describes the algorithm used for detection of the brand string. Processor brand identification software should execute this algorithm on all Intel 64 and IA-32 processors.</p>
<p>This method (introduced with Pentium 4 processors) returns an ASCII brand identification string and the Processor Base frequency of the processor to the EAX, EBX, ECX, and EDX registers.</p>
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<text y="157168.556051" x="165.1203" style="font-size:8.927600pt" lengthAdjust="spacingAndGlyphs" textLength="58.8329152">≥ 0x80000004)</text>
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<h3>Figure 3-9.  Determination of Support for the Processor Brand String</h3>
<h2>How Brand Strings Work</h2>
<p>To use the brand string method, execute CPUID with EAX input of 8000002H through 80000004H. For each input value, CPUID returns 16 ASCII characters using EAX, EBX, ECX, and EDX. The returned string will be NULL-termi-nated.</p>
<p>Table 3-13 shows the brand string that is returned by the first processor in the Pentium 4 processor family.</p>
<h3>Table 3-13.  Processor Brand String Returned with Pentium 4 Processor</h3>
<table>
<tr>
<th>EAX Input Value</th>
<th>Return Values</th>
<th>ASCII Equivalent</th></tr>
<tr>
<td>80000002H</td>
<td>
<p>EAX = 20202020H</p>
<p>EBX = 20202020H</p>
<p>ECX = 20202020H</p>
<p>EDX = 6E492020H</p></td>
<td>
<p>“</p>
<p> ”</p>
<p>“</p>
<p>”</p>
<p>“</p>
<p>”</p>
<p>“nI  ”</p></td></tr>
<tr>
<td>80000003H</td>
<td>
<p>EAX = 286C6574H</p>
<p>EBX = 50202952H</p>
<p>ECX = 69746E65H</p>
<p>EDX = 52286D75H</p></td>
<td>
<p>“(let”</p>
<p>“P )R”</p>
<p>“itne”</p>
<p>“R(mu”</p></td></tr>
<tr>
<td>80000004H</td>
<td>
<p>EAX = 20342029H</p>
<p>EBX = 20555043H</p>
<p>ECX = 30303531H</p>
<p>EDX = 007A484DH</p></td>
<td>
<p>“ 4 )”</p>
<p>“ UPC”</p>
<p>“0051”</p>
<p>“\0zHM”</p></td></tr></table>
<h2>Extracting the Processor Frequency from Brand Strings</h2>
<p>Figure 3-10 provides an algorithm which software can use to extract the Processor Base frequency from the processor brand string.</p>
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<text y="157997.065402" x="170.34" style="font-size:7.280400pt" lengthAdjust="spacingAndGlyphs" textLength="71.93981652">Scan "Brand String" in</text>
<text y="158005.825202" x="174.0603" style="font-size:7.280400pt" lengthAdjust="spacingAndGlyphs" textLength="64.64485572">Reverse Byte Order</text>
<text y="158022.385402" x="171.54" style="font-size:7.280400pt" lengthAdjust="spacingAndGlyphs" textLength="30.62573064">"zHM", or</text>
<text y="158026.765202" x="210.48" style="font-size:7.280400pt" lengthAdjust="spacingAndGlyphs" textLength="19.8900528">Match</text>
<text y="158031.085502" x="171.8997" style="font-size:7.280400pt" lengthAdjust="spacingAndGlyphs" textLength="30.26899104">"zHG", or</text>
<text y="158035.585402" x="210.48" style="font-size:7.280400pt" lengthAdjust="spacingAndGlyphs" textLength="30.91112232">Substring</text>
<text y="158039.965402" x="183.6" style="font-size:7.280400pt" lengthAdjust="spacingAndGlyphs" textLength="18.54609096">"zHT"</text>
<text y="158064.865402" x="287.58" style="font-size:7.280400pt" lengthAdjust="spacingAndGlyphs" textLength="17.90395968">False</text>
<text y="158071.705402" x="171.72" style="font-size:7.280400pt" lengthAdjust="spacingAndGlyphs" textLength="69.49797036">IF Substring Matched</text>
<text y="158071.705402" x="354.36" style="font-size:7.280400pt" lengthAdjust="spacingAndGlyphs" textLength="40.29046164">Report Error</text>
<text y="158109.745402" x="146.4" style="font-size:7.280400pt" lengthAdjust="spacingAndGlyphs" textLength="55.8006258">Determine "Freq"</text>
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<text y="158113.225402" x="209.9397" style="font-size:7.280400pt" lengthAdjust="spacingAndGlyphs" textLength="15.0922692">True</text>
<text y="158116.225302" x="356.7" style="font-size:7.280400pt" lengthAdjust="spacingAndGlyphs" textLength="57.32441352">Multiplier = 1 x 106</text>
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<text y="158136.685402" x="356.7" style="font-size:7.280400pt" lengthAdjust="spacingAndGlyphs" textLength="57.32441352">Multiplier = 1 x 109</text>
<text y="158150.605402" x="171.36" style="font-size:7.280400pt" lengthAdjust="spacingAndGlyphs" textLength="69.93261024">Determine "Multiplier"</text>
<text y="158151.685702" x="291.36" style="font-size:7.280400pt" lengthAdjust="spacingAndGlyphs" textLength="24.61284828">If "zHT"</text>
<text y="158157.145302" x="355.38" style="font-size:7.280400pt" lengthAdjust="spacingAndGlyphs" textLength="57.37100808">Multiplier = 1 x 1012</text>
<text y="158182.885402" x="273.66" style="font-size:7.280400pt" lengthAdjust="spacingAndGlyphs" textLength="36.9917124">Scan Digits</text>
<text y="158191.645202" x="274.68" style="font-size:7.280400pt" lengthAdjust="spacingAndGlyphs" textLength="34.94592">Until Blank</text>
<text y="158195.185402" x="363.0" style="font-size:7.280400pt" lengthAdjust="spacingAndGlyphs" textLength="47.62692072">Reverse Digits</text>
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<text y="158203.945202" x="357.9001" style="font-size:7.280400pt" lengthAdjust="spacingAndGlyphs" textLength="57.69717">To Decimal Value</text>
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<text y="158249.065302" x="185.9999" style="font-size:7.280400pt" lengthAdjust="spacingAndGlyphs" textLength="40.6683144">Frequency =</text>
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<text y="158284.384057" x="430.86" style="font-size:5.460200pt" lengthAdjust="spacingAndGlyphs" textLength="23.85452176">OM15195</text>
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<h3>Figure 3-10.  Algorithm for Extracting Processor Frequency</h3>
<h2>The Processor Brand Index Method</h2>
<p>The brand index method (introduced with Pentium<sup>®</sup> III Xeon<sup>®</sup> processors) provides an entry point into a brand identification table that is maintained in memory by system software and is accessible from system- and user-level code. In this table, each brand index is associate with an ASCII brand identification string that identifies the official Intel family and model number of a processor.</p>
<p>When CPUID executes with EAX set to 1, the processor returns a brand index to the low byte in EBX. Software can then use this index to locate the brand identification string for the processor in the brand identification table. The first entry (brand index 0) in this table is reserved, allowing for backward compatibility with processors that do not support the brand identification feature. Starting with processor signature family ID = 0FH, model = 03H, brand index method is no longer supported. Use brand string method instead.</p>
<p>Table 3-14 shows brand indices that have identification strings associated with them.</p>
<h3>Table 3-14.  Mapping of Brand Indices; and Intel 64 and IA-32 Processor Brand Strings</h3>
<table>
<tr>
<th>Brand Index</th>
<th>Brand String</th></tr>
<tr>
<td>00H</td>
<td>This processor does not support the brand identification feature</td></tr>
<tr>
<td>01H</td>
<td>Intel(R) Celeron(R) processor<sup>1</sup></td></tr>
<tr>
<td>02H</td>
<td>Intel(R) Pentium(R) III processor<sup>1</sup></td></tr>
<tr>
<td>03H</td>
<td>Intel(R) Pentium(R) III Xeon(R) processor; If processor signature = 000006B1h, then Intel(R) Celeron(R) processor</td></tr>
<tr>
<td>04H</td>
<td>Intel(R) Pentium(R) III processor</td></tr>
<tr>
<td>06H</td>
<td>Mobile Intel(R) Pentium(R) III processor-M</td></tr>
<tr>
<td>07H</td>
<td>Mobile Intel(R) Celeron(R) processor<sup>1</sup></td></tr>
<tr>
<td>08H</td>
<td>Intel(R) Pentium(R) 4 processor</td></tr>
<tr>
<td>09H</td>
<td>Intel(R) Pentium(R) 4 processor</td></tr>
<tr>
<td>0AH</td>
<td>Intel(R) Celeron(R) processor<sup>1</sup></td></tr>
<tr>
<td>0BH</td>
<td>Intel(R) Xeon(R) processor; If processor signature = 00000F13h, then Intel(R) Xeon(R) processor MP</td></tr>
<tr>
<td>0CH</td>
<td>Intel(R) Xeon(R) processor MP</td></tr>
<tr>
<td>0EH</td>
<td>Mobile Intel(R) Pentium(R) 4 processor-M; If processor signature = 00000F13h, then Intel(R) Xeon(R) processor</td></tr>
<tr>
<td>0FH</td>
<td>Mobile Intel(R) Celeron(R) processor<sup>1</sup></td></tr>
<tr>
<td>11H</td>
<td>Mobile Genuine Intel(R) processor</td></tr>
<tr>
<td>12H</td>
<td>Intel(R) Celeron(R) M processor</td></tr>
<tr>
<td>13H</td>
<td>Mobile Intel(R) Celeron(R) processor<sup>1</sup></td></tr>
<tr>
<td>14H</td>
<td>Intel(R) Celeron(R) processor</td></tr>
<tr>
<td>15H</td>
<td>Mobile Genuine Intel(R) processor</td></tr>
<tr>
<td>16H</td>
<td>Intel(R) Pentium(R) M processor</td></tr>
<tr>
<td>17H</td>
<td>Mobile Intel(R) Celeron(R) processor<sup>1</sup></td></tr>
<tr>
<td>18H – 0FFH</td>
<td>RESERVED</td></tr></table>
<p>NOTES:</p>
<p>1.</p>
<p>Indicates versions of these processors that were introduced after the Pentium III</p>
<h2>IA-32 Architecture Compatibility</h2>
<p>CPUID is not supported in early models of the Intel486 processor or in any IA-32 processor earlier than the Intel486 processor.</p>
<h2>Operation</h2>
<pre>IA32_BIOS_SIGN_ID MSR ← Update with installed microcode revision number;
CASE (EAX) OF
    EAX = 0:
         EAX ← Highest basic function input value understood by CPUID;
         EBX ← Vendor identification string;
         EDX ← Vendor identification string;
         ECX ← Vendor identification string;
    BREAK;
    EAX = 1H:
         EAX[3:0] ← Stepping ID;
         EAX[7:4] ← Model;
         EAX[11:8] ← Family;
         EAX[13:12] ← Processor type;
         EAX[15:14] ← Reserved;
         EAX[19:16] ← Extended Model;
         EAX[27:20] ← Extended Family;
         EAX[31:28] ← Reserved;
         EBX[7:0] ← Brand Index; (* Reserved if the value is zero. *)
         EBX[15:8] ← CLFLUSH Line Size;
         EBX[16:23] ← Reserved; (* Number of threads enabled = 2 if MT enable fuse set. *)
         EBX[24:31] ← Initial APIC ID;
         ECX ← Feature flags; (* See Figure 3-7. *)
         EDX ← Feature flags; (* See Figure 3-8. *)
    BREAK;
    EAX = 2H:
         EAX ← Cache and TLB information;
         EBX ← Cache and TLB information;
         ECX ← Cache and TLB information;
         EDX ← Cache and TLB information;
    BREAK;
    EAX = 3H:
         EAX ← Reserved;
         EBX ← Reserved;
         ECX ← ProcessorSerialNumber[31:0];
         (* Pentium III processors only, otherwise reserved. *)
         EDX ← ProcessorSerialNumber[63:32];
         (* Pentium III processors only, otherwise reserved. *
    BREAK
    EAX = 4H:
         EAX ← Deterministic Cache Parameters Leaf; (* See Table 3-8. *)
         EBX ← Deterministic Cache Parameters Leaf;
         ECX ← Deterministic Cache Parameters Leaf;
         EDX ← Deterministic Cache Parameters Leaf;
    BREAK;
    EAX = 5H:
         EAX ← MONITOR/MWAIT Leaf; (* See Table 3-8. *)
         EBX ← MONITOR/MWAIT Leaf;
         ECX ← MONITOR/MWAIT Leaf;
         EDX ← MONITOR/MWAIT Leaf;
    BREAK;
    EAX = 6H:
         EAX ← Thermal and Power Management Leaf; (* See Table 3-8. *)
         EBX ← Thermal and Power Management Leaf;
         ECX ← Thermal and Power Management Leaf;
         EDX ← Thermal and Power Management Leaf;
    BREAK;
    EAX = 7H:
         EAX ← Structured Extended Feature Flags Enumeration Leaf; (* See Table 3-8. *)
         EBX ← Structured Extended Feature Flags Enumeration Leaf;
         ECX ← Structured Extended Feature Flags Enumeration Leaf;
         EDX ← Structured Extended Feature Flags Enumeration Leaf;
    BREAK;
    EAX = 8H:
         EAX ← Reserved = 0;
         EBX ← Reserved = 0;
         ECX ← Reserved = 0;
         EDX ← Reserved = 0;
    BREAK;
    EAX = 9H:
         EAX ← Direct Cache Access Information Leaf; (* See Table 3-8. *)
         EBX ← Direct Cache Access Information Leaf;
         ECX ← Direct Cache Access Information Leaf;
         EDX ← Direct Cache Access Information Leaf;
    BREAK;
    EAX = AH:
         EAX ← Architectural Performance Monitoring Leaf; (* See Table 3-8. *)
         EBX ← Architectural Performance Monitoring Leaf;
         ECX ← Architectural Performance Monitoring Leaf;
         EDX ← Architectural Performance Monitoring Leaf;
         BREAK
    EAX = BH:
         EAX ← Extended Topology Enumeration Leaf; (* See Table 3-8. *)
         EBX ← Extended Topology Enumeration Leaf;
         ECX ← Extended Topology Enumeration Leaf;
         EDX ← Extended Topology Enumeration Leaf;
    BREAK;
    EAX = CH:
         EAX ← Reserved = 0;
         EBX ← Reserved = 0;
         ECX ← Reserved = 0;
         EDX ← Reserved = 0;
    BREAK;
    EAX = DH:
         EAX ← Processor Extended State Enumeration Leaf; (* See Table 3-8. *)
         EBX ← Processor Extended State Enumeration Leaf;
         ECX ← Processor Extended State Enumeration Leaf;
         EDX ← Processor Extended State Enumeration Leaf;
    BREAK;
    EAX = EH:
         EAX ← Reserved = 0;
         EBX ← Reserved = 0;
         ECX ← Reserved = 0;
         EDX ← Reserved = 0;
    BREAK;
    EAX = FH:
         EAX ← Intel Resource Director Technology Monitoring Enumeration Leaf; (* See Table 3-8. *)
         EBX ← Intel Resource Director Technology Monitoring Enumeration Leaf;
         ECX ← Intel Resource Director Technology Monitoring Enumeration Leaf;
         EDX ← Intel Resource Director Technology Monitoring Enumeration Leaf;
    BREAK;
    EAX = 10H:
         EAX ← Intel Resource Director Technology Allocation Enumeration Leaf; (* See Table 3-8. *)
         EBX ← Intel Resource Director Technology Allocation Enumeration Leaf;
         ECX ← Intel Resource Director Technology Allocation Enumeration Leaf;
         EDX ← Intel Resource Director Technology Allocation Enumeration Leaf;
    BREAK;
         EAX = 12H:
         EAX ← Intel SGX Enumeration Leaf; (* See Table 3-8. *)
         EBX ← Intel SGX Enumeration Leaf;
         ECX ← Intel SGX Enumeration Leaf;
         EDX ← Intel SGX Enumeration Leaf;
    BREAK;</pre>
<p>EAX = 14H:</p>
<p>EAX ← Intel Processor Trace Enumeration Leaf; (* See Table 3-8. *) EBX ← Intel Processor Trace Enumeration Leaf; ECX ← Intel Processor Trace Enumeration Leaf; EDX ← Intel Processor Trace Enumeration Leaf;</p>
<pre>    BREAK;
    EAX = 15H:
         EAX ← Time Stamp Counter/Core Crystal Clock Information Leaf; (* See Table 3-8. *)
         EBX ← Time Stamp Counter/Core Crystal Clock Information Leaf;
         ECX ← Time Stamp Counter/Core Crystal Clock Information Leaf;
         EDX ← Time Stamp Counter/Core Crystal Clock Information Leaf;
    BREAK;</pre>
<p>EAX = 16H:</p>
<p>EAX ← Processor Frequency Information Enumeration Leaf; (* See Table 3-8. *) EBX ← Processor Frequency Information Enumeration Leaf; ECX ← Processor Frequency Information Enumeration Leaf; EDX ← Processor Frequency Information Enumeration Leaf;</p>
<pre>    BREAK;</pre>
<p>EAX = 17H:</p>
<p>EAX ← System-On-Chip Vendor Attribute Enumeration Leaf; (* See Table 3-8. *) EBX ← System-On-Chip Vendor Attribute Enumeration Leaf; ECX ← System-On-Chip Vendor Attribute Enumeration Leaf; EDX ← System-On-Chip Vendor Attribute Enumeration Leaf;</p>
<pre>    BREAK;
    EAX = 80000000H:
         EAX ← Highest extended function input value understood by CPUID;
         EBX ← Reserved;
         ECX ← Reserved;
         EDX ← Reserved;
    BREAK;
    EAX = 80000001H:
         EAX ← Reserved;
         EBX ← Reserved;
         ECX ← Extended Feature Bits (* See Table 3-8.*);
         EDX ← Extended Feature Bits (* See Table 3-8. *);
    BREAK;
    EAX = 80000002H:
         EAX ← Processor Brand String;
         EBX ← Processor Brand String, continued;
         ECX ← Processor Brand String, continued;
         EDX ← Processor Brand String, continued;
    BREAK;
    EAX = 80000003H:
         EAX ← Processor Brand String, continued;
         EBX ← Processor Brand String, continued;
         ECX ← Processor Brand String, continued;
         EDX ← Processor Brand String, continued;
    BREAK;
    EAX = 80000004H:
         EAX ← Processor Brand String, continued;
         EBX ← Processor Brand String, continued;
         ECX ← Processor Brand String, continued;
         EDX ← Processor Brand String, continued;
    BREAK;
    EAX = 80000005H:
         EAX ← Reserved = 0;
         EBX ← Reserved = 0;
         ECX ← Reserved = 0;
         EDX ← Reserved = 0;
    BREAK;
    EAX = 80000006H:
         EAX ← Reserved = 0;
         EBX ← Reserved = 0;
         ECX ← Cache information;
         EDX ← Reserved = 0;
    BREAK;
    EAX = 80000007H:
         EAX ← Reserved = 0;
         EBX ← Reserved = 0;
         ECX ← Reserved = 0;
         EDX ← Reserved = Misc Feature Flags;
    BREAK;
    EAX = 80000008H:
         EAX ← Reserved = Physical Address Size Information;
         EBX ← Reserved = Virtual Address Size Information;
         ECX ← Reserved = 0;
         EDX ← Reserved = 0;
    BREAK;
    EAX &gt;= 40000000H and EAX &lt;= 4FFFFFFFH:
    DEFAULT: (* EAX = Value outside of recognized range for CPUID. *)
         (* If the highest basic information leaf data depend on ECX input value, ECX is honored.*)
         EAX ← Reserved; (* Information returned for highest basic information leaf. *)
         EBX ← Reserved; (* Information returned for highest basic information leaf. *)
         ECX ← Reserved; (* Information returned for highest basic information leaf. *)
         EDX ← Reserved; (* Information returned for highest basic information leaf. *)
    BREAK;
ESAC;</pre>
<h2>Flags Affected</h2>
<p>None.</p>
<h2>Exceptions (All Operating Modes)</h2>
<p>#UD</p>
<p>If the LOCK prefix is used.</p>
<p>In earlier IA-32 processors that do not support the CPUID instruction, execution of the instruc-tion results in an invalid opcode (#UD) exception being generated.</p></body></html>